1 /* 2 * Copyright 2007 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Eric Anholt <eric (at) anholt.net> 25 * 26 */ 27 28 #define PCI_CHIP_I810 0x7121 29 #define PCI_CHIP_I810_DC100 0x7123 30 #define PCI_CHIP_I810_E 0x7125 31 #define PCI_CHIP_I815 0x1132 32 33 #define PCI_CHIP_I830_M 0x3577 34 #define PCI_CHIP_845_G 0x2562 35 #define PCI_CHIP_I855_GM 0x3582 36 #define PCI_CHIP_I865_G 0x2572 37 38 #define PCI_CHIP_I915_G 0x2582 39 #define PCI_CHIP_E7221_G 0x258A 40 #define PCI_CHIP_I915_GM 0x2592 41 #define PCI_CHIP_I945_G 0x2772 42 #define PCI_CHIP_I945_GM 0x27A2 43 #define PCI_CHIP_I945_GME 0x27AE 44 45 #define PCI_CHIP_Q35_G 0x29B2 46 #define PCI_CHIP_G33_G 0x29C2 47 #define PCI_CHIP_Q33_G 0x29D2 48 49 #define PCI_CHIP_IGD_GM 0xA011 50 #define PCI_CHIP_IGD_G 0xA001 51 52 #define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM) 53 #define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G) 54 #define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) 55 56 #define PCI_CHIP_I965_G 0x29A2 57 #define PCI_CHIP_I965_Q 0x2992 58 #define PCI_CHIP_I965_G_1 0x2982 59 #define PCI_CHIP_I946_GZ 0x2972 60 #define PCI_CHIP_I965_GM 0x2A02 61 #define PCI_CHIP_I965_GME 0x2A12 62 63 #define PCI_CHIP_GM45_GM 0x2A42 64 65 #define PCI_CHIP_IGD_E_G 0x2E02 66 #define PCI_CHIP_Q45_G 0x2E12 67 #define PCI_CHIP_G45_G 0x2E22 68 #define PCI_CHIP_G41_G 0x2E32 69 #define PCI_CHIP_B43_G 0x2E42 70 #define PCI_CHIP_B43_G1 0x2E92 71 72 #define PCI_CHIP_ILD_G 0x0042 73 #define PCI_CHIP_ILM_G 0x0046 74 75 #define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */ 76 #define PCI_CHIP_SANDYBRIDGE_GT2 0x0112 77 #define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122 78 #define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */ 79 #define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116 80 #define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126 81 #define PCI_CHIP_SANDYBRIDGE_S 0x010A /* Server */ 82 83 #define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */ 84 #define PCI_CHIP_IVYBRIDGE_GT2 0x0162 85 #define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */ 86 #define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166 87 #define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */ 88 #define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a 89 90 #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */ 91 #define PCI_CHIP_HASWELL_GT2 0x0412 92 #define PCI_CHIP_HASWELL_GT2_PLUS 0x0422 93 #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */ 94 #define PCI_CHIP_HASWELL_M_GT2 0x0416 95 #define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426 96 #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */ 97 #define PCI_CHIP_HASWELL_S_GT2 0x041A 98 #define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A 99 #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */ 100 #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12 101 #define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22 102 #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */ 103 #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16 104 #define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26 105 #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */ 106 #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A 107 #define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A 108 #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */ 109 #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12 110 #define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22 111 #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */ 112 #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16 113 #define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26 114 #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */ 115 #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A 116 #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A 117 #define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */ 118 #define PCI_CHIP_HASWELL_CRW_GT2 0x0D22 119 #define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32 120 #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */ 121 #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26 122 #define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36 123 #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */ 124 #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A 125 #define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A 126 127 #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ 128 devid == PCI_CHIP_I915_GM || \ 129 devid == PCI_CHIP_I945_GM || \ 130 devid == PCI_CHIP_I945_GME || \ 131 devid == PCI_CHIP_I965_GM || \ 132 devid == PCI_CHIP_I965_GME || \ 133 devid == PCI_CHIP_GM45_GM || \ 134 IS_IGD(devid) || \ 135 devid == PCI_CHIP_ILM_G) 136 137 #define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \ 138 devid == PCI_CHIP_Q45_G || \ 139 devid == PCI_CHIP_G45_G || \ 140 devid == PCI_CHIP_G41_G || \ 141 devid == PCI_CHIP_B43_G || \ 142 devid == PCI_CHIP_B43_G1) 143 #define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM) 144 #define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid)) 145 146 #define IS_ILD(devid) (devid == PCI_CHIP_ILD_G) 147 #define IS_ILM(devid) (devid == PCI_CHIP_ILM_G) 148 #define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid)) 149 150 #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ 151 devid == PCI_CHIP_E7221_G || \ 152 devid == PCI_CHIP_I915_GM) 153 154 #define IS_945(devid) (devid == PCI_CHIP_I945_G || \ 155 devid == PCI_CHIP_I945_GM || \ 156 devid == PCI_CHIP_I945_GME || \ 157 devid == PCI_CHIP_G33_G || \ 158 devid == PCI_CHIP_Q33_G || \ 159 devid == PCI_CHIP_Q35_G || IS_IGD(devid)) 160 161 #define IS_GEN4(devid) (devid == PCI_CHIP_I965_G || \ 162 devid == PCI_CHIP_I965_Q || \ 163 devid == PCI_CHIP_I965_G_1 || \ 164 devid == PCI_CHIP_I965_GM || \ 165 devid == PCI_CHIP_I965_GME || \ 166 devid == PCI_CHIP_I946_GZ || \ 167 IS_G4X(devid)) 168 169 /* Compat macro for intel_decode.c */ 170 #define IS_IRONLAKE(devid) IS_GEN5(devid) 171 172 #define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \ 173 devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \ 174 devid == PCI_CHIP_SANDYBRIDGE_S) 175 176 #define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \ 177 devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \ 178 devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \ 179 devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS) 180 181 #define IS_GEN6(devid) (IS_SNB_GT1(devid) || IS_SNB_GT2(devid)) 182 183 #define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \ 184 devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \ 185 devid == PCI_CHIP_IVYBRIDGE_S_GT1) 186 187 #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \ 188 devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ 189 devid == PCI_CHIP_IVYBRIDGE_S_GT2) 190 191 #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid)) 192 193 #define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \ 194 IS_HASWELL(devid)) 195 196 #define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \ 197 devid == PCI_CHIP_HASWELL_M_GT1 || \ 198 devid == PCI_CHIP_HASWELL_S_GT1 || \ 199 devid == PCI_CHIP_HASWELL_SDV_GT1 || \ 200 devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \ 201 devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \ 202 devid == PCI_CHIP_HASWELL_ULT_GT1 || \ 203 devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \ 204 devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \ 205 devid == PCI_CHIP_HASWELL_CRW_GT1 || \ 206 devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \ 207 devid == PCI_CHIP_HASWELL_CRW_S_GT1) 208 #define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2 || \ 209 devid == PCI_CHIP_HASWELL_M_GT2 || \ 210 devid == PCI_CHIP_HASWELL_S_GT2 || \ 211 devid == PCI_CHIP_HASWELL_SDV_GT2 || \ 212 devid == PCI_CHIP_HASWELL_SDV_M_GT2 || \ 213 devid == PCI_CHIP_HASWELL_SDV_S_GT2 || \ 214 devid == PCI_CHIP_HASWELL_ULT_GT2 || \ 215 devid == PCI_CHIP_HASWELL_ULT_M_GT2 || \ 216 devid == PCI_CHIP_HASWELL_ULT_S_GT2 || \ 217 devid == PCI_CHIP_HASWELL_CRW_GT2 || \ 218 devid == PCI_CHIP_HASWELL_CRW_M_GT2 || \ 219 devid == PCI_CHIP_HASWELL_CRW_S_GT2 || \ 220 devid == PCI_CHIP_HASWELL_M_GT2_PLUS || \ 221 devid == PCI_CHIP_HASWELL_S_GT2_PLUS || \ 222 devid == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \ 223 devid == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \ 224 devid == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \ 225 devid == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \ 226 devid == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \ 227 devid == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \ 228 devid == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \ 229 devid == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \ 230 devid == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS) 231 232 #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \ 233 IS_HSW_GT2(devid)) 234 235 #define IS_965(devid) (IS_GEN4(devid) || \ 236 IS_G4X(devid) || \ 237 IS_GEN5(devid) || \ 238 IS_GEN6(devid) || \ 239 IS_GEN7(devid)) 240 241 #define IS_9XX(devid) (IS_915(devid) || \ 242 IS_945(devid) || \ 243 IS_965(devid)) 244 245 #define IS_GEN3(devid) (IS_915(devid) || \ 246 IS_945(devid)) 247 248 #define IS_GEN2(devid) (devid == PCI_CHIP_I830_M || \ 249 devid == PCI_CHIP_845_G || \ 250 devid == PCI_CHIP_I855_GM || \ 251 devid == PCI_CHIP_I865_G) 252
