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    Searched defs:PR (Results 1 - 25 of 29) sorted by null

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  /external/clang/test/SemaCXX/
access-control-check.cpp 14 int PR() { return iP + PPR(); } // expected-error 2 {{private member of 'P'}}
  /external/clang/test/CodeGenCXX/
nested-base-member-access.cpp 38 void PR() {
51 n1.PR();
constructor-init.cpp 36 void PR() {
61 n1.PR();
  /external/llvm/lib/Target/AMDGPU/
AMDGPUTargetMachine.cpp 46 PassRegistry *PR = PassRegistry::getPassRegistry();
47 initializeSILowerI1CopiesPass(*PR);
48 initializeSIFixSGPRCopiesPass(*PR);
49 initializeSIFoldOperandsPass(*PR);
50 initializeSIFixSGPRLiveRangesPass(*PR);
51 initializeSIFixControlFlowLiveIntervalsPass(*PR);
52 initializeSILoadStoreOptimizerPass(*PR);
53 initializeAMDGPUAnnotateKernelFeaturesPass(*PR);
54 initializeAMDGPUAnnotateUniformValuesPass(*PR);
  /external/llvm/lib/Target/NVPTX/
NVPTXTargetMachine.cpp 68 PassRegistry &PR = *PassRegistry::getPassRegistry();
69 initializeNVVMReflectPass(PR);
70 initializeGenericToNVVMPass(PR);
71 initializeNVPTXAllocaHoistingPass(PR);
72 initializeNVPTXAssignValidGlobalNamesPass(PR);
73 initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
74 initializeNVPTXLowerKernelArgsPass(PR);
75 initializeNVPTXLowerAllocaPass(PR);
76 initializeNVPTXLowerAggrCopiesPass(PR);
  /external/llvm/lib/Target/X86/
X86TargetMachine.cpp 40 PassRegistry &PR = *PassRegistry::getPassRegistry();
41 initializeWinEHStatePassPass(PR);
  /device/google/contexthub/firmware/src/platform/stm32f4xx/
exti.c 31 volatile uint32_t PR;
63 EXTI->PR = (1UL << line);
68 return (EXTI->PR & (1UL << line)) ? true : false;
  /toolchain/binutils/binutils-2.25/opcodes/
rl78-dis.c 101 #define PR (dis->fprintf_func)
103 #define PC(c) PR (PS, "%c", c)
197 PR (PS, " \033[33mW\033[0m");
204 PR (PS, " \033[35m");
207 { PR (PS, "Z"); comma = ","; }
209 { PR (PS, "%sAC", comma); comma = ","; }
211 { PR (PS, "%sCY", comma); comma = ","; }
212 PR (PS, "\033[0m");
224 PR (PS, "es:");
232 PR (PS, "%s", condition_names[oper->condition])
    [all...]
rx-dis.c 103 #define PR (dis->fprintf_func)
105 #define PC(c) PR (PS, "%c", c)
145 PR (PS, "%s", opsize_names[opcode.size]);
155 PR (PS, "%s", size_names[oper->size]);
166 PR (PS, "%#x", oper->addend);
168 PR (PS, "%d", oper->addend);
172 PR (PS, "%s", register_names[oper->reg]);
176 PR (PS, "%d[%s]", oper->addend, register_names[oper->reg]);
178 PR (PS, "[%s]", register_names[oper->reg]);
181 PR (PS, "[%s+]", register_names[oper->reg])
    [all...]
ia64-opc.h 53 #define PR IA64_OPND_PR
  /external/llvm/lib/CodeGen/
RegisterScavenging.cpp 61 BitVector PR = MF.getFrameInfo()->getPristineRegs(MF);
62 for (int I = PR.find_first(); I>0; I = PR.find_next(I))
Passes.cpp 521 const PassRegistry *PR = PassRegistry::getPassRegistry();
522 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
523 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
MachineVerifier.cpp 707 BitVector PR = MFI->getPristineRegs(*MF);
708 for (int I = PR.find_first(); I>0; I = PR.find_next(I)) {
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 270 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
285 unsigned PSrc = MI->getOperand(PR).getReg();
287 MI->getOperand(PR).setReg(POrig);
HexagonGenMux.cpp 72 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR,
75 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1),
209 unsigned PR = MI->getOperand(1).getReg();
216 if (F != CM.end() && F->second.PredR != PR) {
223 F->second.PredR = PR;
244 if (!DU.Defs[PR])
268 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) {
285 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2));
HexagonGenPredicate.cpp 52 friend raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR);
57 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR)
59 raw_ostream &operator<< (raw_ostream &OS, const PrintRegister &PR) {
60 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
241 Register PR = DefI->getOperand(1);
242 G2P.insert(std::make_pair(Reg, PR));
243 DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n');
244 return PR;
    [all...]
HexagonSplitDouble.cpp 469 unsigned PR = Cond[1].getReg();
470 assert(MRI->getRegClass(PR) == &Hexagon::PredRegsRegClass);
475 const MachineInstr *CmpI = MRI->getVRegDef(PR);
    [all...]
HexagonFrameLowering.cpp 164 PassRegistry &PR = *PassRegistry::getPassRegistry();
165 initializeHexagonCallFrameInformationPass(PR);
    [all...]
  /external/llvm/lib/Target/PowerPC/
PPCTargetMachine.cpp 75 PassRegistry &PR = *PassRegistry::getPassRegistry();
76 initializePPCBoolRetToIntPass(PR);
  /external/llvm/tools/llc/
llc.cpp 350 const PassRegistry *PR = PassRegistry::getPassRegistry();
357 const PassInfo *PI = PR->getPassInfo(RunPass);
365 const PassInfo *PI = PR->getPassInfo(StartAfter);
373 const PassInfo *PI = PR->getPassInfo(StopAfter);
  /dalvik/docs/
prettify.js 68 var PR;
    [all...]
  /external/opencv/cvaux/src/
cvsegment.cpp 123 int k, YC, PL, PR, flag/*, curstep*/;
125 POP( YC, L, R, PL, PR, flag );
127 int data[][3] = { {-flag, L, R}, {flag, L, PL-1}, {flag,PR+1,R}};
  /external/opencv/cv/src/
cvfloodfill.cpp 144 int k, YC, PL, PR, dir;
145 ICV_POP( YC, L, R, PL, PR, dir );
151 {dir, PR + 1, R + _8_connectivity}
276 int k, YC, PL, PR, dir;
277 ICV_POP( YC, L, R, PL, PR, dir );
283 {dir, PR + 1, R + _8_connectivity}
453 int k, YC, PL, PR, dir, curstep;
454 ICV_POP( YC, L, R, PL, PR, dir );
460 {dir, PR + 1, R + _8_connectivity}
759 int k, YC, PL, PR, dir, curstep
    [all...]
  /external/opencv3/modules/imgproc/src/
floodfill.cpp 160 int k, YC, PL, PR, dir;
161 ICV_POP( YC, L, R, PL, PR, dir );
167 {dir, PR + 1, R + _8_connectivity}
330 int k, YC, PL, PR, dir;
331 ICV_POP( YC, L, R, PL, PR, dir );
337 {dir, PR + 1, R + _8_connectivity}
  /libcore/luni/src/test/java/libcore/java/util/
EnumSetTest.java 104 IN, SN, SB, TE, I, XE, CS, BA, LA, CE, PR, ND, PM, SM, EU, GD, TB, DY, HO, ER, TM, YB, LU,

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