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  /external/llvm/utils/TableGen/
CodeGenSchedule.h 99 IdxVec ProcIndices;
109 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
113 /// subtargets. ProcIndices contains 0 for any processor.
117 /// instructions to this class. ProcIndices contains all the processors that
122 /// resolved at runtime. ProcIndices contains the set of processors that may
123 /// require the class. ProcIndices are propagated through SchedClasses as
135 IdxVec ProcIndices;
367 ArrayRef<unsigned> ProcIndices);
403 unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
415 ArrayRef<unsigned> ProcIndices);
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SubtargetEmitter.cpp 839 if (TI->ProcIndices[0] == 0) {
843 IdxIter PIPos = std::find(TI->ProcIndices.begin(),
844 TI->ProcIndices.end(), ProcModel.Index);
845 if (PIPos != TI->ProcIndices.end()) {
857 // If ProcIndices contains 0, this class applies to all processors.
858 assert(!SCI->ProcIndices.empty() && "expect at least one procidx");
859 if (SCI->ProcIndices[0] != 0) {
860 IdxIter PIPos = std::find(SCI->ProcIndices.begin(),
861 SCI->ProcIndices.end(), ProcModel.Index);
862 if (PIPos == SCI->ProcIndices.end()
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