1 /****************************************************************************** 2 * 3 * Copyright (C) 2015 The Android Open Source Project 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at: 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 * 17 ***************************************************************************** 18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore 19 */ 20 /*! 21 ************************************************************************** 22 * \file ih264d_utils.c 23 * 24 * \brief 25 * Contains routines that handle of start and end of pic processing 26 * 27 * \date 28 * 19/12/2002 29 * 30 * \author AI 31 ************************************************************************** 32 */ 33 34 #include <string.h> 35 #include "ih264_typedefs.h" 36 #include "ithread.h" 37 #include "ih264d_deblocking.h" 38 #include "ih264d_parse_slice.h" 39 #include "ih264d_parse_cavlc.h" 40 #include "ih264d_dpb_manager.h" 41 #include "ih264d_defs.h" 42 #include "ih264d_structs.h" 43 #include "ih264d_mem_request.h" 44 #include "ih264_typedefs.h" 45 #include "ih264_macros.h" 46 #include "ih264_platform_macros.h" 47 #include "ih264d_tables.h" 48 #include "ih264d_debug.h" 49 #include "ih264d_mb_utils.h" 50 #include "ih264d_error_handler.h" 51 #include "ih264d_dpb_manager.h" 52 #include "ih264d_utils.h" 53 #include "ih264d_defs.h" 54 #include "ih264d_tables.h" 55 #include "ih264d_inter_pred.h" 56 #include "ih264d_dpb_manager.h" 57 #include "iv.h" 58 #include "ivd.h" 59 #include "ih264d_format_conv.h" 60 #include "ih264_error.h" 61 #include "ih264_disp_mgr.h" 62 #include "ih264_buf_mgr.h" 63 #include "ih264d_utils.h" 64 65 /*! 66 ************************************************************************** 67 * \if Function name : ih264d_is_end_of_pic \endif 68 * 69 * \brief 70 * Determines whether current slice is first slice of a new picture as 71 * defined in 7.4.1.2.4 of 14496-10. 72 * 73 * \return 74 * Return 1 if current slice is first slice of a new picture 75 * Otherwise it returns 0 76 ************************************************************************** 77 */ 78 UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num, 79 UWORD8 u1_nal_ref_idc, 80 pocstruct_t *ps_cur_poc, 81 pocstruct_t *ps_prev_poc, 82 dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/ 83 UWORD8 u1_pic_order_cnt_type, 84 UWORD8 u1_nal_unit_type, 85 UWORD32 u4_idr_pic_id, 86 UWORD8 u1_field_pic_flag, 87 UWORD8 u1_bottom_field_flag) 88 { 89 WORD8 i1_is_end_of_pic; 90 WORD8 a, b, c, d, e, f, g, h; 91 92 a = b = c = d = e = f = g = h = 0; 93 a = (ps_prev_slice->u2_frame_num != u2_frame_num); 94 b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag); 95 if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag) 96 c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag); 97 d = 98 (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0) 99 || (u1_nal_ref_idc != 0 100 && ps_prev_slice->u1_nal_ref_idc 101 == 0); 102 if(!a) 103 { 104 if((u1_pic_order_cnt_type == 0) 105 && (ps_prev_slice->u1_pic_order_cnt_type == 0)) 106 { 107 e = 108 ((ps_cur_poc->i4_pic_order_cnt_lsb 109 != ps_prev_poc->i4_pic_order_cnt_lsb) 110 || (ps_cur_poc->i4_delta_pic_order_cnt_bottom 111 != ps_prev_poc->i4_delta_pic_order_cnt_bottom)); 112 } 113 114 if((u1_pic_order_cnt_type == 1) 115 && (ps_prev_slice->u1_pic_order_cnt_type == 1)) 116 { 117 f = 118 ((ps_cur_poc->i4_delta_pic_order_cnt[0] 119 != ps_prev_poc->i4_delta_pic_order_cnt[0]) 120 || (ps_cur_poc->i4_delta_pic_order_cnt[1] 121 != ps_prev_poc->i4_delta_pic_order_cnt[1])); 122 } 123 } 124 125 if((u1_nal_unit_type == IDR_SLICE_NAL) 126 && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL)) 127 { 128 g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id); 129 } 130 131 if((u1_nal_unit_type == IDR_SLICE_NAL) 132 && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL)) 133 { 134 h = 1; 135 } 136 i1_is_end_of_pic = a + b + c + d + e + f + g + h; 137 return (i1_is_end_of_pic); 138 } 139 140 /*! 141 ************************************************************************** 142 * \if Function name : ih264d_decode_pic_order_cnt \endif 143 * 144 * \brief 145 * Calculates picture order count of picture. 146 * 147 * \return 148 * Returns the pic order count of the picture to which current 149 * Slice belongs. 150 * 151 ************************************************************************** 152 */ 153 WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice, 154 UWORD32 u2_frame_num, 155 pocstruct_t *ps_prev_poc, 156 pocstruct_t *ps_cur_poc, 157 dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/ 158 dec_pic_params_t * ps_pps, 159 UWORD8 u1_nal_ref_idc, 160 UWORD8 u1_bottom_field_flag, 161 UWORD8 u1_field_pic_flag, 162 WORD32 *pi4_poc) 163 { 164 WORD16 i1_pic_msb; 165 WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0; 166 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 167 WORD32 i4_prev_frame_num_ofst; 168 169 switch(ps_seq->u1_pic_order_cnt_type) 170 { 171 case 0: 172 /* POC TYPE 0 */ 173 if(u1_is_idr_slice) 174 { 175 ps_prev_poc->i4_pic_order_cnt_msb = 0; 176 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 177 } 178 if(ps_prev_poc->u1_mmco_equalto5) 179 { 180 if(ps_prev_poc->u1_bot_field != 1) 181 { 182 ps_prev_poc->i4_pic_order_cnt_msb = 0; 183 ps_prev_poc->i4_pic_order_cnt_lsb = 184 ps_prev_poc->i4_top_field_order_count; 185 } 186 else 187 { 188 ps_prev_poc->i4_pic_order_cnt_msb = 0; 189 ps_prev_poc->i4_pic_order_cnt_lsb = 0; 190 } 191 } 192 193 if((ps_cur_poc->i4_pic_order_cnt_lsb 194 < ps_prev_poc->i4_pic_order_cnt_lsb) 195 && ((ps_prev_poc->i4_pic_order_cnt_lsb 196 - ps_cur_poc->i4_pic_order_cnt_lsb) 197 >= (ps_seq->i4_max_pic_order_cntLsb 198 >> 1))) 199 { 200 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 201 + ps_seq->i4_max_pic_order_cntLsb; 202 } 203 else if((ps_cur_poc->i4_pic_order_cnt_lsb 204 > ps_prev_poc->i4_pic_order_cnt_lsb) 205 && ((ps_cur_poc->i4_pic_order_cnt_lsb 206 - ps_prev_poc->i4_pic_order_cnt_lsb) 207 >= (ps_seq->i4_max_pic_order_cntLsb 208 >> 1))) 209 { 210 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb 211 - ps_seq->i4_max_pic_order_cntLsb; 212 } 213 else 214 { 215 i1_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb; 216 } 217 218 if(!u1_field_pic_flag || !u1_bottom_field_flag) 219 i4_top_field_order_cnt = i1_pic_msb 220 + ps_cur_poc->i4_pic_order_cnt_lsb; 221 222 if(!u1_field_pic_flag) 223 { 224 i4_bottom_field_order_cnt = i4_top_field_order_cnt 225 + ps_cur_poc->i4_delta_pic_order_cnt_bottom; 226 } 227 else if(u1_bottom_field_flag) 228 { 229 i4_bottom_field_order_cnt = i1_pic_msb 230 + ps_cur_poc->i4_pic_order_cnt_lsb; 231 } 232 ps_cur_poc->i4_pic_order_cnt_msb = i1_pic_msb; 233 break; 234 235 case 1: 236 { 237 /* POC TYPE 1 */ 238 UWORD8 i; 239 WORD32 prev_frame_num; 240 WORD32 frame_num_ofst; 241 WORD32 abs_frm_num; 242 WORD32 poc_cycle_cnt, frame_num_in_poc_cycle; 243 WORD32 expected_delta_poc_cycle; 244 WORD32 expected_poc; 245 246 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 247 if(!u1_is_idr_slice) 248 { 249 if(ps_cur_slice->u1_mmco_equalto5) 250 { 251 prev_frame_num = 0; 252 i4_prev_frame_num_ofst = 0; 253 } 254 else 255 { 256 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 257 } 258 } 259 else 260 i4_prev_frame_num_ofst = 0; 261 262 /* 1. Derivation for FrameNumOffset */ 263 if(u1_is_idr_slice) 264 { 265 frame_num_ofst = 0; 266 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 267 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 268 } 269 else if(prev_frame_num > ((WORD32)u2_frame_num)) 270 { 271 frame_num_ofst = i4_prev_frame_num_ofst 272 + ps_seq->u2_u4_max_pic_num_minus1 + 1; 273 } 274 else 275 frame_num_ofst = i4_prev_frame_num_ofst; 276 277 /* 2. Derivation for absFrameNum */ 278 if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle) 279 abs_frm_num = frame_num_ofst + u2_frame_num; 280 else 281 abs_frm_num = 0; 282 if((u1_nal_ref_idc == 0) && (abs_frm_num > 0)) 283 abs_frm_num = abs_frm_num - 1; 284 285 /* 4. expectedDeltaPerPicOrderCntCycle is derived as */ 286 expected_delta_poc_cycle = 0; 287 for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle; 288 i++) 289 { 290 expected_delta_poc_cycle += 291 ps_seq->i4_ofst_for_ref_frame[i]; 292 } 293 294 /* 3. When absFrameNum > 0, picOrderCntCycleCnt and 295 frame_num_in_poc_cycle are derived as : */ 296 /* 5. expectedPicOrderCnt is derived as : */ 297 if(abs_frm_num > 0) 298 { 299 poc_cycle_cnt = 300 DIV((abs_frm_num - 1), 301 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 302 frame_num_in_poc_cycle = 303 MOD((abs_frm_num - 1), 304 ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle); 305 306 expected_poc = poc_cycle_cnt 307 * expected_delta_poc_cycle; 308 for(i = 0; i <= frame_num_in_poc_cycle; i++) 309 { 310 expected_poc = expected_poc 311 + ps_seq->i4_ofst_for_ref_frame[i]; 312 } 313 } 314 else 315 expected_poc = 0; 316 317 if(u1_nal_ref_idc == 0) 318 { 319 expected_poc = expected_poc 320 + ps_seq->i4_ofst_for_non_ref_pic; 321 } 322 323 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 324 if(!u1_field_pic_flag) 325 { 326 i4_top_field_order_cnt = expected_poc 327 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 328 i4_bottom_field_order_cnt = i4_top_field_order_cnt 329 + ps_seq->i4_ofst_for_top_to_bottom_field 330 + ps_cur_poc->i4_delta_pic_order_cnt[1]; 331 } 332 else if(!u1_bottom_field_flag) 333 { 334 i4_top_field_order_cnt = expected_poc 335 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 336 } 337 else 338 { 339 i4_bottom_field_order_cnt = expected_poc 340 + ps_seq->i4_ofst_for_top_to_bottom_field 341 + ps_cur_poc->i4_delta_pic_order_cnt[0]; 342 } 343 /* Copy the current POC info into Previous POC structure */ 344 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 345 } 346 347 break; 348 case 2: 349 { 350 /* POC TYPE 2 */ 351 WORD32 prev_frame_num; 352 WORD32 frame_num_ofst; 353 WORD32 tmp_poc; 354 355 prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num; 356 if(!u1_is_idr_slice) 357 { 358 if(ps_cur_slice->u1_mmco_equalto5) 359 { 360 prev_frame_num = 0; 361 i4_prev_frame_num_ofst = 0; 362 } 363 else 364 i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst; 365 } 366 else 367 i4_prev_frame_num_ofst = 0; 368 369 /* 1. Derivation for FrameNumOffset */ 370 if(u1_is_idr_slice) 371 { 372 frame_num_ofst = 0; 373 ps_cur_poc->i4_delta_pic_order_cnt[0] = 0; 374 ps_cur_poc->i4_delta_pic_order_cnt[1] = 0; 375 } 376 else if(prev_frame_num > ((WORD32)u2_frame_num)) 377 { 378 frame_num_ofst = i4_prev_frame_num_ofst 379 + ps_seq->u2_u4_max_pic_num_minus1 + 1; 380 } 381 else 382 frame_num_ofst = i4_prev_frame_num_ofst; 383 384 /* 2. Derivation for tempPicOrderCnt */ 385 if(u1_is_idr_slice) 386 tmp_poc = 0; 387 else if(u1_nal_ref_idc == 0) 388 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1) 389 - 1; 390 else 391 tmp_poc = ((frame_num_ofst + u2_frame_num) << 1); 392 393 /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */ 394 if(!u1_field_pic_flag) 395 { 396 i4_top_field_order_cnt = tmp_poc; 397 i4_bottom_field_order_cnt = tmp_poc; 398 } 399 else if(!u1_bottom_field_flag) 400 i4_top_field_order_cnt = tmp_poc; 401 else 402 i4_bottom_field_order_cnt = tmp_poc; 403 404 /* Copy the current POC info into Previous POC structure */ 405 ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst; 406 ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst; 407 } 408 break; 409 default: 410 return ERROR_INV_POC_TYPE_T; 411 break; 412 } 413 414 if(!u1_field_pic_flag) // or a complementary field pair 415 { 416 *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt); 417 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 418 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 419 } 420 else if(!u1_bottom_field_flag) 421 { 422 *pi4_poc = i4_top_field_order_cnt; 423 ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt; 424 } 425 else 426 { 427 *pi4_poc = i4_bottom_field_order_cnt; 428 ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt; 429 } 430 431 ps_pps->i4_avg_poc = *pi4_poc; 432 433 return OK; 434 } 435 436 /*! 437 ************************************************************************** 438 * \if Function name : ih264d_end_of_pic_processing \endif 439 * 440 * \brief 441 * Performs the end of picture processing. 442 * 443 * It performs deblocking on the current picture and sets the i4_status of 444 * current picture as decoded. 445 * 446 * \return 447 * 0 on Success and Error code otherwise. 448 ************************************************************************** 449 */ 450 WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec) 451 { 452 UWORD8 u1_pic_type, u1_nal_ref_idc; 453 dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice; 454 WORD32 ret; 455 456 /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL 457 unit of a particular picture, it shall be equal to 0 for all slice and 458 slice data partition NAL units of the picture. nal_ref_idc greater 459 than 0 indicates that the content of the NAL unit belongs to a decoded 460 picture that is stored and marked for use as a reference picture in the 461 decoded picture buffer. */ 462 463 /* 1. Do MMCO 464 2. Add Cur Pic to list of reference pics. 465 */ 466 467 /* Call MMCO */ 468 u1_pic_type = 0; 469 u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc; 470 471 if(u1_nal_ref_idc) 472 { 473 if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL) 474 { 475 if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0) 476 { 477 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 478 479 { 480 ret = ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 481 ps_dec->ps_cur_pic, 482 ps_dec->u1_pic_buf_id, 483 ps_cur_slice->u2_frame_num); 484 if(ret != OK) 485 return ret; 486 } 487 } 488 else 489 { 490 /* Equivalent of inserting a pic directly as longterm Pic */ 491 492 { 493 ret = ih264d_insert_st_node(ps_dec->ps_dpb_mgr, 494 ps_dec->ps_cur_pic, 495 ps_dec->u1_pic_buf_id, 496 ps_cur_slice->u2_frame_num); 497 if(ret != OK) 498 return ret; 499 /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */ 500 ret = ih264d_delete_st_node_or_make_lt( 501 ps_dec->ps_dpb_mgr, 502 ps_cur_slice->u2_frame_num, 0, 503 ps_cur_slice->u1_field_pic_flag); 504 if(ret != OK) 505 return ret; 506 ps_dec->ps_dpb_mgr->u1_max_lt_pic_idx_plus1 = 1; 507 } 508 } 509 } 510 else 511 { 512 513 { 514 UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num; 515 516 517 518 ret = ih264d_do_mmco_buffer( 519 ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr, 520 ps_dec->ps_cur_sps->u1_num_ref_frames, 521 u2_pic_num, 522 (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1), 523 ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic, 524 ps_dec->u1_pic_buf_id, 525 ps_cur_slice->u1_field_pic_flag, 526 ps_dec->e_dec_status); 527 if(ret != OK) 528 return ret; 529 } 530 } 531 ih264d_update_default_index_list(ps_dec->ps_dpb_mgr); 532 } 533 534 if(ps_cur_slice->u1_field_pic_flag) 535 { 536 if(ps_cur_slice->u1_bottom_field_flag) 537 { 538 if(u1_nal_ref_idc) 539 u1_pic_type = u1_pic_type | BOT_REF; 540 u1_pic_type = u1_pic_type | BOT_FLD; 541 } 542 else 543 { 544 if(u1_nal_ref_idc) 545 u1_pic_type = u1_pic_type | TOP_REF; 546 u1_pic_type = u1_pic_type | TOP_FLD; 547 } 548 } 549 else 550 u1_pic_type = TOP_REF | BOT_REF; 551 ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type; 552 553 554 if(ps_cur_slice->u1_field_pic_flag) 555 { 556 H264_DEC_DEBUG_PRINT("Toggling secondField\n"); 557 ps_dec->u1_second_field = 1 - ps_dec->u1_second_field; 558 } 559 560 return OK; 561 } 562 563 /*****************************************************************************/ 564 /* */ 565 /* Function Name : init_dpb_size */ 566 /* */ 567 /* Description : This function calculates the DBP i4_size in frames */ 568 /* Inputs : ps_seq - current sequence params */ 569 /* */ 570 /* Globals : None */ 571 /* */ 572 /* Outputs : None */ 573 /* */ 574 /* Returns : DPB in frames */ 575 /* */ 576 /* Issues : None */ 577 /* */ 578 /* Revision History: */ 579 /* */ 580 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 581 /* 28 04 2005 NS Draft */ 582 /* */ 583 /*****************************************************************************/ 584 WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq) 585 { 586 WORD32 i4_size; 587 UWORD8 u1_level_idc; 588 589 u1_level_idc = ps_seq->u1_level_idc; 590 591 switch(u1_level_idc) 592 { 593 case 10: 594 i4_size = 152064; 595 break; 596 case 11: 597 i4_size = 345600; 598 break; 599 case 12: 600 i4_size = 912384; 601 break; 602 case 13: 603 i4_size = 912384; 604 break; 605 case 20: 606 i4_size = 912384; 607 break; 608 case 21: 609 i4_size = 1824768; 610 break; 611 case 22: 612 i4_size = 3110400; 613 break; 614 case 30: 615 i4_size = 3110400; 616 break; 617 case 31: 618 i4_size = 6912000; 619 break; 620 case 32: 621 i4_size = 7864320; 622 break; 623 case 40: 624 i4_size = 12582912; 625 break; 626 case 41: 627 i4_size = 12582912; 628 break; 629 case 42: 630 i4_size = 12582912; 631 break; 632 case 50: 633 i4_size = 42393600; 634 break; 635 case 51: 636 i4_size = 70778880; 637 break; 638 case 52: 639 i4_size = 70778880; 640 break; 641 default: 642 i4_size = 70778880; 643 break; 644 } 645 646 i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag))); 647 i4_size /= 384; 648 i4_size = MIN(i4_size, 16); 649 i4_size = MAX(i4_size, 1); 650 return (i4_size); 651 } 652 653 /***************************************************************************/ 654 /* If change in Level or the required PicBuffers i4_size is more than the */ 655 /* current one FREE the current PicBuffers and allocate affresh */ 656 /***************************************************************************/ 657 UWORD8 ih264d_is_sps_changed(prev_seq_params_t * ps_prv, 658 dec_seq_params_t * ps_cur) 659 { 660 661 if((ps_prv->u2_frm_wd_in_mbs != ps_cur->u2_frm_wd_in_mbs) 662 || (ps_prv->u1_level_idc != ps_cur->u1_level_idc) 663 || (ps_prv->u1_profile_idc != ps_cur->u1_profile_idc) 664 || (ps_cur->u2_frm_ht_in_mbs != ps_prv->u2_frm_ht_in_mbs) 665 || (ps_cur->u1_frame_mbs_only_flag 666 != ps_prv->u1_frame_mbs_only_flag) 667 || (ps_cur->u1_direct_8x8_inference_flag 668 != ps_prv->u1_direct_8x8_inference_flag)) 669 return 1; 670 671 return 0; 672 } 673 674 /**************************************************************************/ 675 /* This function initialises the value of ps_dec->u1_recon_mb_grp */ 676 /* ps_dec->u1_recon_mb_grp must satisfy the following criteria */ 677 /* - multiple of 2 (required for N/2 parse-mvpred design) */ 678 /* - multiple of 4 (if it is not a frame_mbs_only sequence), */ 679 /* in this case N/2 itself needs to be even for mbpair processing */ 680 /* - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks */ 681 /* should make a row to ensure proper MvTop transferring) */ 682 /**************************************************************************/ 683 WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec) 684 { 685 dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps; 686 UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag; 687 688 ps_dec->u1_recon_mb_grp = PARSE_MB_GROUP_4; 689 690 //NMB set to width in MBs for non-mbaff cases 691 if(0 == ps_seq->u1_mb_aff_flag) 692 ps_dec->u1_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs; 693 694 ps_dec->u1_recon_mb_grp_pair = ps_dec->u1_recon_mb_grp >> 1; 695 696 if(!ps_dec->u1_recon_mb_grp) 697 { 698 return ERROR_MB_GROUP_ASSGN_T; 699 } 700 701 ps_dec->u4_num_mbs_prev_nmb = ps_dec->u1_recon_mb_grp; 702 703 return OK; 704 } 705 706 707 /*! 708 ************************************************************************** 709 * \if Function name : ih264d_init_pic \endif 710 * 711 * \brief 712 * Initializes the picture. 713 * 714 * \return 715 * 0 on Success and Error code otherwise 716 * 717 * \note 718 * This function is called when first slice of the 719 * NON -IDR picture is encountered. 720 ************************************************************************** 721 */ 722 WORD32 ih264d_init_pic(dec_struct_t *ps_dec, 723 UWORD16 u2_frame_num, 724 WORD32 i4_poc, 725 dec_pic_params_t *ps_pps) 726 { 727 dec_seq_params_t *ps_seq = ps_pps->ps_sps; 728 prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params; 729 WORD32 i4_pic_bufs; 730 WORD32 ret; 731 732 ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num; 733 ps_dec->ps_cur_slice->i4_poc = i4_poc; 734 ps_dec->ps_cur_pps = ps_pps; 735 ps_dec->ps_cur_pps->pv_codec_handle = ps_dec; 736 737 ps_dec->ps_cur_sps = ps_seq; 738 ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1 739 + 1; 740 741 ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht; 742 ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd; 743 ps_dec->i4_pic_type = -1; 744 ps_dec->i4_frametype = -1; 745 ps_dec->i4_content_type = -1; 746 747 /*--------------------------------------------------------------------*/ 748 /* Get the value of MaxMbAddress and frmheight in Mbs */ 749 /*--------------------------------------------------------------------*/ 750 ps_seq->u2_max_mb_addr = 751 (ps_seq->u2_frm_wd_in_mbs 752 * (ps_dec->u2_pic_ht 753 >> (4 754 + ps_dec->ps_cur_slice->u1_field_pic_flag))) 755 - 1; 756 ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht 757 >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag)); 758 759 /***************************************************************************/ 760 /* If change in Level or the required PicBuffers i4_size is more than the */ 761 /* current one FREE the current PicBuffers and allocate affresh */ 762 /***************************************************************************/ 763 if(!ps_dec->u1_init_dec_flag 764 || ih264d_is_sps_changed(ps_prev_seq_params, ps_seq)) 765 { 766 ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq); 767 768 ps_dec->i4_display_delay = ps_dec->u1_max_dec_frame_buffering; 769 if((1 == ps_seq->u1_vui_parameters_present_flag) && 770 (1 == ps_seq->s_vui.u1_bitstream_restriction_flag)) 771 { 772 if(ps_seq->u1_frame_mbs_only_flag == 1) 773 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames + 1; 774 else 775 ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames * 2 + 2; 776 } 777 778 if(IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode) 779 ps_dec->i4_display_delay = 0; 780 781 if(ps_dec->u4_share_disp_buf == 0) 782 { 783 if(ps_seq->u1_frame_mbs_only_flag == 1) 784 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames + 1; 785 else 786 ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + ps_seq->u1_num_ref_frames * 2 + 2; 787 } 788 else 789 { 790 ps_dec->u1_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs; 791 } 792 793 /* Ensure at least two buffers are allocated */ 794 ps_dec->u1_pic_bufs = MAX(ps_dec->u1_pic_bufs, 2); 795 796 if(ps_dec->u4_share_disp_buf == 0) 797 ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs, 798 (H264_MAX_REF_PICS * 2)); 799 800 ps_dec->u1_max_dec_frame_buffering = MIN( 801 ps_dec->u1_max_dec_frame_buffering, 802 ps_dec->u1_pic_bufs); 803 804 /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams also for CAFI1_SVA_C.264 in conformance*/ 805 if(ps_dec->u1_init_dec_flag) 806 { 807 ih264d_release_pics_in_dpb((void *)ps_dec, 808 ps_dec->u1_pic_bufs); 809 ih264d_release_display_bufs(ps_dec); 810 ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr); 811 } 812 813 /*********************************************************************/ 814 /* Configuring decoder parameters based on level and then */ 815 /* fresh pointer initialisation in decoder scratch and state buffers */ 816 /*********************************************************************/ 817 if(!ps_dec->u1_init_dec_flag || 818 ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0))) 819 { 820 ret = ih264d_init_dec_mb_grp(ps_dec); 821 if(ret != OK) 822 return ret; 823 } 824 825 ret = ih264d_allocate_dynamic_bufs(ps_dec); 826 if(ret != OK) 827 { 828 /* Free any dynamic buffers that are allocated */ 829 ih264d_free_dynamic_bufs(ps_dec); 830 ps_dec->i4_error_code = IVD_MEM_ALLOC_FAILED; 831 return IVD_MEM_ALLOC_FAILED; 832 } 833 834 ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs, 835 ps_dec); 836 if(ret != OK) 837 return ret; 838 839 840 841 ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd, 842 ps_dec->u2_pic_ht); 843 if(ret != OK) 844 return ret; 845 846 /* In shared mode, set all of them as used by display */ 847 if(ps_dec->u4_share_disp_buf == 1) 848 { 849 WORD32 i; 850 851 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 852 { 853 ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 854 BUF_MGR_IO); 855 } 856 } 857 858 ps_dec->u1_init_dec_flag = 1; 859 ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs; 860 ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc; 861 ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc; 862 ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs; 863 ps_prev_seq_params->u1_frame_mbs_only_flag = 864 ps_seq->u1_frame_mbs_only_flag; 865 ps_prev_seq_params->u1_direct_8x8_inference_flag = 866 ps_seq->u1_direct_8x8_inference_flag; 867 868 ps_dec->i4_cur_display_seq = 0; 869 ps_dec->i4_prev_max_display_seq = 0; 870 ps_dec->i4_max_poc = 0; 871 872 { 873 /* 0th entry of CtxtIncMbMap will be always be containing default values 874 for CABAC context representing MB not available */ 875 ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1; 876 UWORD8 *pu1_temp; 877 WORD8 i; 878 p_DefCtxt->u1_mb_type = CAB_SKIP; 879 880 p_DefCtxt->u1_cbp = 0x0f; 881 p_DefCtxt->u1_intra_chroma_pred_mode = 0; 882 883 p_DefCtxt->u1_yuv_dc_csbp = 0x7; 884 885 p_DefCtxt->u1_transform8x8_ctxt = 0; 886 887 pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx; 888 for(i = 0; i < 4; i++, pu1_temp++) 889 (*pu1_temp) = 0; 890 pu1_temp = (UWORD8*)p_DefCtxt->u1_mv; 891 for(i = 0; i < 16; i++, pu1_temp++) 892 (*pu1_temp) = 0; 893 ps_dec->ps_def_ctxt_mb_info = p_DefCtxt; 894 } 895 896 } 897 /* reset DBP commands read u4_flag */ 898 ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0; 899 900 return OK; 901 } 902 903 /*****************************************************************************/ 904 /* */ 905 /* Function Name : ih264d_get_next_display_field */ 906 /* */ 907 /* Description : Application calls this module to get the next field */ 908 /* to be displayed */ 909 /* */ 910 /* Inputs : 1. IBUFAPI_Handle Hnadle to the Display buffer */ 911 /* 2. IH264DEC_DispUnit Pointer to the display struct */ 912 /* */ 913 /* Globals : */ 914 /* */ 915 /* */ 916 /* Processing : None */ 917 /* Outputs : None */ 918 /* Returns : None */ 919 /* Issues : None */ 920 /* */ 921 /* Revision History: */ 922 /* */ 923 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 924 /* 27 05 2005 Ittiam Draft */ 925 /* */ 926 /*****************************************************************************/ 927 928 WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec, 929 ivd_out_bufdesc_t *ps_out_buffer, 930 ivd_get_display_frame_op_t *pv_disp_op) 931 { 932 pic_buffer_t *pic_buf; 933 934 UWORD8 i1_cur_fld; 935 WORD32 u4_api_ret = -1; 936 WORD32 i4_disp_buf_id; 937 iv_yuv_buf_t *ps_op_frm; 938 939 940 941 ps_op_frm = &(ps_dec->s_disp_frame_info); 942 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 943 pic_buf = (pic_buffer_t *)ih264_disp_mgr_get( 944 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id); 945 ps_dec->u4_num_fld_in_frm = 0; 946 u4_api_ret = -1; 947 pv_disp_op->u4_ts = -1; 948 pv_disp_op->e_output_format = ps_dec->u1_chroma_format; 949 950 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0]; 951 pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1]; 952 pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2]; 953 if(pic_buf != NULL) 954 { 955 pv_disp_op->e4_fld_type = 0; 956 pv_disp_op->u4_disp_buf_id = i4_disp_buf_id; 957 958 ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1; 959 ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1; 960 ps_op_frm->u4_y_wd = pic_buf->u2_disp_width; 961 962 ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1; 963 964 ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y; 965 ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv; 966 967 /* ! */ 968 pv_disp_op->u4_ts = pic_buf->u4_ts; 969 970 /* set the start of the Y, U and V buffer pointer for display */ 971 ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y; 972 ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv; 973 ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv; 974 ps_dec->u4_num_fld_in_frm++; 975 ps_dec->u4_num_fld_in_frm++; 976 u4_api_ret = 0; 977 978 if(pic_buf->u1_picturetype == 0) 979 pv_disp_op->u4_progressive_frame_flag = 1; 980 else 981 pv_disp_op->u4_progressive_frame_flag = 0; 982 983 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 984 pv_disp_op->u4_error_code = u4_api_ret; 985 pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk; 986 987 if(u4_api_ret) 988 { 989 pv_disp_op->u4_error_code = 1; //put a proper error code here 990 } 991 else 992 { 993 994 //Release the buffer if being sent for display 995 UWORD32 temp; 996 UWORD32 dest_inc_Y = 0, dest_inc_UV = 0; 997 998 pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd, 999 ps_op_frm->u4_y_strd); 1000 pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 1001 >> 1; 1002 pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd 1003 >> 1; 1004 1005 pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht; 1006 pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 1007 >> 1; 1008 pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht 1009 >> 1; 1010 if(0 == ps_dec->u4_share_disp_buf) 1011 { 1012 pv_disp_op->s_disp_frm_buf.u4_y_strd = 1013 pv_disp_op->s_disp_frm_buf.u4_y_wd; 1014 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1015 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 1016 pv_disp_op->s_disp_frm_buf.u4_v_strd = 1017 pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1; 1018 1019 } 1020 else 1021 { 1022 pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd; 1023 } 1024 1025 if(ps_dec->u4_app_disp_width) 1026 { 1027 pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX( 1028 ps_dec->u4_app_disp_width, 1029 pv_disp_op->s_disp_frm_buf.u4_y_strd); 1030 } 1031 1032 pv_disp_op->u4_error_code = 0; 1033 if(pv_disp_op->e_output_format == IV_YUV_420P) 1034 { 1035 UWORD32 i; 1036 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1037 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1038 pv_disp_op->s_disp_frm_buf.u4_v_strd = 1039 pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1; 1040 1041 pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1; 1042 pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1; 1043 1044 if(1 == ps_dec->u4_share_disp_buf) 1045 { 1046 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1047 1048 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1049 { 1050 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1051 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1052 if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1053 - pic_buf->u2_crop_offset_y) == buf) 1054 { 1055 buf = ps_dec->disp_bufs[i].buf[1]; 1056 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1057 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1058 + pic_buf->u2_crop_offset_uv; 1059 1060 buf = ps_dec->disp_bufs[i].buf[2]; 1061 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1062 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1063 + pic_buf->u2_crop_offset_uv; 1064 } 1065 } 1066 } 1067 1068 } 1069 else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV) 1070 || (pv_disp_op->e_output_format == IV_YUV_420SP_VU)) 1071 { 1072 pv_disp_op->s_disp_frm_buf.u4_u_strd = 1073 pv_disp_op->s_disp_frm_buf.u4_y_strd; 1074 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1075 1076 if(1 == ps_dec->u4_share_disp_buf) 1077 { 1078 UWORD32 i; 1079 1080 pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf; 1081 1082 for(i = 0; i < MAX_DISP_BUFS_NEW; i++) 1083 { 1084 UWORD8 *buf = ps_dec->disp_bufs[i].buf[0]; 1085 buf += ps_dec->disp_bufs[i].u4_ofst[0]; 1086 if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf 1087 - pic_buf->u2_crop_offset_y == buf) 1088 { 1089 buf = ps_dec->disp_bufs[i].buf[1]; 1090 buf += ps_dec->disp_bufs[i].u4_ofst[1]; 1091 pv_disp_op->s_disp_frm_buf.pv_u_buf = buf 1092 + pic_buf->u2_crop_offset_uv; 1093 ; 1094 1095 buf = ps_dec->disp_bufs[i].buf[2]; 1096 buf += ps_dec->disp_bufs[i].u4_ofst[2]; 1097 pv_disp_op->s_disp_frm_buf.pv_v_buf = buf 1098 + pic_buf->u2_crop_offset_uv; 1099 ; 1100 } 1101 } 1102 } 1103 pv_disp_op->s_disp_frm_buf.u4_u_wd = 1104 pv_disp_op->s_disp_frm_buf.u4_y_wd; 1105 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1106 1107 } 1108 else if((pv_disp_op->e_output_format == IV_RGB_565) 1109 || (pv_disp_op->e_output_format == IV_YUV_422ILE)) 1110 { 1111 1112 pv_disp_op->s_disp_frm_buf.u4_u_strd = 0; 1113 pv_disp_op->s_disp_frm_buf.u4_v_strd = 0; 1114 pv_disp_op->s_disp_frm_buf.u4_u_wd = 0; 1115 pv_disp_op->s_disp_frm_buf.u4_v_wd = 0; 1116 pv_disp_op->s_disp_frm_buf.u4_u_ht = 0; 1117 pv_disp_op->s_disp_frm_buf.u4_v_ht = 0; 1118 1119 } 1120 1121 1122 } 1123 1124 return u4_api_ret; 1125 } 1126 1127 1128 /*****************************************************************************/ 1129 /* Function Name : ih264d_release_display_field */ 1130 /* */ 1131 /* Description : This function releases the display field that was returned */ 1132 /* here. */ 1133 /* Inputs : ps_dec - Decoder parameters */ 1134 /* Globals : None */ 1135 /* Processing : Refer bumping process in the standard */ 1136 /* Outputs : Assigns display sequence number. */ 1137 /* Returns : None */ 1138 /* */ 1139 /* Issues : None */ 1140 /* */ 1141 /* Revision History: */ 1142 /* */ 1143 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1144 /* 27 04 2005 NS Draft */ 1145 /* */ 1146 /*****************************************************************************/ 1147 void ih264d_release_display_field(dec_struct_t *ps_dec, 1148 ivd_get_display_frame_op_t *pv_disp_op) 1149 { 1150 if(1 == pv_disp_op->u4_error_code) 1151 { 1152 if(1 == ps_dec->u1_flushfrm) 1153 { 1154 UWORD32 i; 1155 1156 if(1 == ps_dec->u4_share_disp_buf) 1157 { 1158 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1159 for(i = 0; i < (MAX_DISP_BUFS_NEW); i++) 1160 { 1161 if(1 == ps_dec->u4_disp_buf_mapping[i]) 1162 { 1163 ih264_buf_mgr_release( 1164 (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i, 1165 BUF_MGR_IO); 1166 ps_dec->u4_disp_buf_mapping[i] = 0; 1167 } 1168 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1169 1170 memset(ps_dec->u4_disp_buf_to_be_freed, 0, 1171 (MAX_DISP_BUFS_NEW) * sizeof(UWORD32)); 1172 for(i = 0; i < ps_dec->u1_pic_bufs; i++) 1173 ps_dec->u4_disp_buf_mapping[i] = 1; 1174 } 1175 ps_dec->u1_flushfrm = 0; 1176 1177 } 1178 } 1179 else 1180 { 1181 H264_MUTEX_LOCK(&ps_dec->process_disp_mutex); 1182 1183 if(0 == ps_dec->u4_share_disp_buf) 1184 { 1185 ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1186 pv_disp_op->u4_disp_buf_id, 1187 BUF_MGR_IO); 1188 1189 } 1190 else 1191 { 1192 ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1; 1193 } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex); 1194 1195 } 1196 } 1197 /*****************************************************************************/ 1198 /* Function Name : ih264d_assign_display_seq */ 1199 /* */ 1200 /* Description : This function implments bumping process. Every outgoing */ 1201 /* frame from DPB is assigned a display sequence number */ 1202 /* which increases monotonically. System looks for this */ 1203 /* number to display a frame. */ 1204 /* here. */ 1205 /* Inputs : ps_dec - Decoder parameters */ 1206 /* Globals : None */ 1207 /* Processing : Refer bumping process in the standard */ 1208 /* Outputs : Assigns display sequence number. */ 1209 /* Returns : None */ 1210 /* */ 1211 /* Issues : None */ 1212 /* */ 1213 /* Revision History: */ 1214 /* */ 1215 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1216 /* 27 04 2005 NS Draft */ 1217 /* */ 1218 /*****************************************************************************/ 1219 WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec) 1220 { 1221 WORD32 i; 1222 WORD32 i4_min_poc; 1223 WORD32 i4_min_poc_buf_id; 1224 WORD32 i4_min_index; 1225 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1226 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1227 1228 i4_min_poc = 0x7fffffff; 1229 i4_min_poc_buf_id = -1; 1230 i4_min_index = -1; 1231 1232 if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay) 1233 { 1234 for(i = 0; i < MAX_FRAMES; i++) 1235 { 1236 if((i4_poc_buf_id_map[i][0] != -1) 1237 && (DO_NOT_DISP 1238 != ps_dpb_mgr->ai4_poc_buf_id_map[i][0])) 1239 { 1240 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1241 { 1242 i4_min_poc = i4_poc_buf_id_map[i][1]; 1243 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1244 i4_min_index = i; 1245 } 1246 } 1247 } 1248 1249 if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id)) 1250 { 1251 ps_dec->i4_cur_display_seq++; 1252 ih264_disp_mgr_add( 1253 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1254 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1255 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1256 i4_poc_buf_id_map[i4_min_index][0] = -1; 1257 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1258 ps_dpb_mgr->i1_poc_buf_id_entries--; 1259 } 1260 else if(DO_NOT_DISP == i4_min_poc_buf_id) 1261 { 1262 WORD32 i4_error_code; 1263 i4_error_code = ERROR_GAPS_IN_FRM_NUM; 1264 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1265 return i4_error_code; 1266 } 1267 } 1268 return OK; 1269 } 1270 1271 /*****************************************************************************/ 1272 /* */ 1273 /* Function Name : ih264d_release_display_bufs */ 1274 /* */ 1275 /* Description : This function implments bumping process when mmco = 5. */ 1276 /* Each outgoing frame from DPB is assigned a display */ 1277 /* sequence number which increases monotonically. System */ 1278 /* looks for this number to display a frame. */ 1279 /* Inputs : ps_dec - Decoder parameters */ 1280 /* Globals : None */ 1281 /* Processing : Refer bumping process in the standard for mmco = 5 */ 1282 /* Outputs : Assigns display sequence number. */ 1283 /* Returns : None */ 1284 /* */ 1285 /* Issues : None */ 1286 /* */ 1287 /* Revision History: */ 1288 /* */ 1289 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1290 /* 27 04 2005 NS Draft */ 1291 /* */ 1292 /*****************************************************************************/ 1293 void ih264d_release_display_bufs(dec_struct_t *ps_dec) 1294 { 1295 WORD32 i, j; 1296 WORD32 i4_min_poc; 1297 WORD32 i4_min_poc_buf_id; 1298 WORD32 i4_min_index; 1299 dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1300 WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map; 1301 1302 i4_min_poc = 0x7fffffff; 1303 i4_min_poc_buf_id = -1; 1304 i4_min_index = -1; 1305 1306 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1307 1308 for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++) 1309 { 1310 i4_min_poc = 0x7fffffff; 1311 for(i = 0; i < MAX_FRAMES; i++) 1312 { 1313 if(i4_poc_buf_id_map[i][0] != -1) 1314 { 1315 if(i4_poc_buf_id_map[i][1] < i4_min_poc) 1316 { 1317 i4_min_poc = i4_poc_buf_id_map[i][1]; 1318 i4_min_poc_buf_id = i4_poc_buf_id_map[i][0]; 1319 i4_min_index = i; 1320 } 1321 } 1322 } 1323 1324 if(DO_NOT_DISP != i4_min_poc_buf_id) 1325 { 1326 ps_dec->i4_cur_display_seq++; 1327 ih264_disp_mgr_add( 1328 (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, 1329 i4_min_poc_buf_id, ps_dec->i4_cur_display_seq, 1330 ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]); 1331 i4_poc_buf_id_map[i4_min_index][0] = -1; 1332 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1333 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1334 } 1335 else 1336 { 1337 i4_poc_buf_id_map[i4_min_index][0] = -1; 1338 i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff; 1339 ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0; 1340 } 1341 } 1342 ps_dpb_mgr->i1_poc_buf_id_entries = 0; 1343 ps_dec->i4_prev_max_display_seq = ps_dec->i4_prev_max_display_seq 1344 + ps_dec->i4_max_poc + ps_dec->u1_max_dec_frame_buffering 1345 + 1; 1346 ps_dec->i4_max_poc = 0; 1347 } 1348 1349 /*****************************************************************************/ 1350 /* */ 1351 /* Function Name : ih264d_assign_pic_num */ 1352 /* */ 1353 /* Description : This function assigns pic num to each reference frame */ 1354 /* depending on the cur_frame_num as speified in section */ 1355 /* 8.2.4.1 */ 1356 /* */ 1357 /* Inputs : ps_dec */ 1358 /* */ 1359 /* Globals : NO globals used */ 1360 /* */ 1361 /* Processing : for all ST pictures */ 1362 /* if( FrameNum > cur_frame_num) */ 1363 /* PicNum = FrameNum - MaxFrameNum */ 1364 /* else */ 1365 /* PicNum = FrameNum */ 1366 /* */ 1367 /* Returns : void */ 1368 /* */ 1369 /* Issues : NO */ 1370 /* */ 1371 /* Revision History: */ 1372 /* */ 1373 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1374 /* 13 07 2002 Jay Draft */ 1375 /* */ 1376 /*****************************************************************************/ 1377 1378 void ih264d_assign_pic_num(dec_struct_t *ps_dec) 1379 { 1380 dpb_manager_t *ps_dpb_mgr; 1381 struct dpb_info_t *ps_next_dpb; 1382 WORD8 i; 1383 WORD32 i4_cur_frame_num, i4_max_frame_num; 1384 WORD32 i4_ref_frame_num; 1385 UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag; 1386 1387 i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1388 i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num; 1389 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1390 1391 /* Start from ST head */ 1392 ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head; 1393 for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++) 1394 { 1395 WORD32 i4_pic_num; 1396 1397 i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num; 1398 if(i4_ref_frame_num > i4_cur_frame_num) 1399 { 1400 /* RefPic Buf frame_num is before Current frame_num in decode order */ 1401 i4_pic_num = i4_ref_frame_num - i4_max_frame_num; 1402 } 1403 else 1404 { 1405 /* RefPic Buf frame_num is after Current frame_num in decode order */ 1406 i4_pic_num = i4_ref_frame_num; 1407 } 1408 1409 ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num; 1410 ps_next_dpb->i4_frame_num = i4_pic_num; 1411 ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1; 1412 if(u1_fld_pic_flag) 1413 { 1414 /* Assign the pic num to top fields and bot fields */ 1415 1416 ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2 1417 + !(ps_dec->ps_cur_slice->u1_bottom_field_flag); 1418 ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2 1419 + ps_dec->ps_cur_slice->u1_bottom_field_flag; 1420 } 1421 /* Chase the next link */ 1422 ps_next_dpb = ps_next_dpb->ps_prev_short; 1423 } 1424 1425 if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag 1426 && ps_dpb_mgr->u1_num_gaps) 1427 { 1428 WORD32 i4_start_frm, i4_end_frm; 1429 /* Assign pic numbers for gaps */ 1430 for(i = 0; i < MAX_FRAMES; i++) 1431 { 1432 i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i]; 1433 if(i4_start_frm != INVALID_FRAME_NUM) 1434 { 1435 if(i4_start_frm > i4_cur_frame_num) 1436 { 1437 /* gap's frame_num is before Current frame_num in 1438 decode order */ 1439 i4_start_frm -= i4_max_frame_num; 1440 } 1441 ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm; 1442 i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i]; 1443 1444 if(i4_end_frm > i4_cur_frame_num) 1445 { 1446 /* gap's frame_num is before Current frame_num in 1447 decode order */ 1448 i4_end_frm -= i4_max_frame_num; 1449 } 1450 ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm; 1451 } 1452 } 1453 } 1454 } 1455 1456 /*! 1457 ************************************************************************** 1458 * \if Function name : ih264d_update_qp \endif 1459 * 1460 * \brief 1461 * Updates the values of QP and its related entities 1462 * 1463 * \return 1464 * 0 on Success and Error code otherwise 1465 * 1466 ************************************************************************** 1467 */ 1468 WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp) 1469 { 1470 WORD32 i_temp; 1471 i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52; 1472 1473 if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25)) 1474 return ERROR_INV_RANGE_QP_T; 1475 1476 ps_dec->u1_qp = i_temp; 1477 ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6; 1478 ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6; 1479 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset); 1480 ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1481 ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1482 1483 i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset); 1484 ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1485 ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6); 1486 1487 ps_dec->pu2_quant_scale_y = 1488 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6]; 1489 ps_dec->pu2_quant_scale_u = 1490 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6]; 1491 ps_dec->pu2_quant_scale_v = 1492 gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6]; 1493 return OK; 1494 } 1495 1496 /*****************************************************************************/ 1497 /* */ 1498 /* Function Name : ih264d_decode_gaps_in_frame_num */ 1499 /* */ 1500 /* Description : This function decodes gaps in frame number */ 1501 /* */ 1502 /* Inputs : ps_dec Decoder parameters */ 1503 /* u2_frame_num current frame number */ 1504 /* */ 1505 /* Globals : None */ 1506 /* Processing : This functionality needs to be implemented */ 1507 /* Outputs : None */ 1508 /* Returns : None */ 1509 /* */ 1510 /* Issues : Not implemented */ 1511 /* */ 1512 /* Revision History: */ 1513 /* */ 1514 /* DD MM YYYY Author(s) Changes (Describe the changes made) */ 1515 /* 06 05 2002 NS Draft */ 1516 /* */ 1517 /*****************************************************************************/ 1518 WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec, 1519 UWORD16 u2_frame_num) 1520 { 1521 UWORD32 u4_next_frm_num, u4_start_frm_num; 1522 UWORD32 u4_max_frm_num; 1523 pocstruct_t s_tmp_poc; 1524 WORD32 i4_poc; 1525 dec_slice_params_t *ps_cur_slice; 1526 1527 dec_pic_params_t *ps_pic_params; 1528 WORD8 i1_gap_idx; 1529 WORD32 *i4_gaps_start_frm_num; 1530 dpb_manager_t *ps_dpb_mgr; 1531 WORD32 i4_frame_gaps; 1532 WORD8 *pi1_gaps_per_seq; 1533 WORD32 ret; 1534 1535 ps_cur_slice = ps_dec->ps_cur_slice; 1536 if(ps_cur_slice->u1_field_pic_flag) 1537 { 1538 if(ps_dec->u2_prev_ref_frame_num == u2_frame_num) 1539 return 0; 1540 } 1541 1542 u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1; 1543 u4_max_frm_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1; 1544 1545 // check 1546 if(u4_next_frm_num >= u4_max_frm_num) 1547 { 1548 u4_next_frm_num -= u4_max_frm_num; 1549 } 1550 1551 if(u4_next_frm_num == u2_frame_num) 1552 { 1553 return (0); 1554 } 1555 1556 // check 1557 if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL) 1558 && (u4_next_frm_num >= u2_frame_num)) 1559 { 1560 return (0); 1561 } 1562 u4_start_frm_num = u4_next_frm_num; 1563 1564 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1565 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1566 s_tmp_poc.i4_pic_order_cnt_lsb = 0; 1567 s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0; 1568 s_tmp_poc.i4_delta_pic_order_cnt[0] = 0; 1569 s_tmp_poc.i4_delta_pic_order_cnt[1] = 0; 1570 1571 ps_cur_slice = ps_dec->ps_cur_slice; 1572 ps_pic_params = ps_dec->ps_cur_pps; 1573 ps_cur_slice->u1_field_pic_flag = 0; 1574 1575 i4_frame_gaps = 0; 1576 ps_dpb_mgr = ps_dec->ps_dpb_mgr; 1577 1578 /* Find a empty slot to store gap seqn info */ 1579 i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num; 1580 for(i1_gap_idx = 0; i1_gap_idx < MAX_FRAMES; i1_gap_idx++) 1581 { 1582 if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx]) 1583 break; 1584 } 1585 if(MAX_FRAMES == i1_gap_idx) 1586 { 1587 UWORD32 i4_error_code; 1588 i4_error_code = ERROR_DBP_MANAGER_T; 1589 // i4_error_code |= 1<<IVD_CORRUPTEDDATA; 1590 return i4_error_code; 1591 } 1592 1593 i4_poc = 0; 1594 i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num; 1595 ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1; 1596 pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq; 1597 pi1_gaps_per_seq[i1_gap_idx] = 0; 1598 while(u4_next_frm_num != u2_frame_num) 1599 { 1600 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1601 if(ps_pic_params->ps_sps->u1_pic_order_cnt_type) 1602 { 1603 /* allocate a picture buffer and insert it as ST node */ 1604 ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num, 1605 &ps_dec->s_prev_pic_poc, 1606 &s_tmp_poc, ps_cur_slice, 1607 ps_pic_params, 1, 0, 0, 1608 &i4_poc); 1609 if(ret != OK) 1610 return ret; 1611 1612 /* Display seq no calculations */ 1613 if(i4_poc >= ps_dec->i4_max_poc) 1614 ps_dec->i4_max_poc = i4_poc; 1615 /* IDR Picture or POC wrap around */ 1616 if(i4_poc == 0) 1617 { 1618 ps_dec->i4_prev_max_display_seq = 1619 ps_dec->i4_prev_max_display_seq 1620 + ps_dec->i4_max_poc 1621 + ps_dec->u1_max_dec_frame_buffering 1622 + 1; 1623 ps_dec->i4_max_poc = 0; 1624 } 1625 1626 ps_cur_slice->u1_mmco_equalto5 = 0; 1627 ps_cur_slice->u2_frame_num = u4_next_frm_num; 1628 } 1629 1630 // check 1631 if(ps_dpb_mgr->i1_poc_buf_id_entries 1632 >= ps_dec->u1_max_dec_frame_buffering) 1633 { 1634 ret = ih264d_assign_display_seq(ps_dec); 1635 if(ret != OK) 1636 return ret; 1637 } 1638 1639 ret = ih264d_insert_pic_in_display_list( 1640 ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP, 1641 (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc), 1642 u4_next_frm_num); 1643 if(ret != OK) 1644 return ret; 1645 1646 pi1_gaps_per_seq[i1_gap_idx]++; 1647 ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr, 1648 ps_dec->ps_cur_sps->u1_num_ref_frames); 1649 if(ret != OK) 1650 return ret; 1651 1652 ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr); 1653 1654 u4_next_frm_num++; 1655 if(u4_next_frm_num >= u4_max_frm_num) 1656 { 1657 u4_next_frm_num -= u4_max_frm_num; 1658 } 1659 1660 i4_frame_gaps++; 1661 } 1662 1663 return OK; 1664 } 1665 1666 /*! 1667 ************************************************************************** 1668 * \if Function name : ih264d_create_pic_buffers \endif 1669 * 1670 * \brief 1671 * This function creates Picture Buffers. 1672 * 1673 * \return 1674 * 0 on Success and -1 on error 1675 ************************************************************************** 1676 */ 1677 WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf, 1678 dec_struct_t *ps_dec) 1679 { 1680 struct pic_buffer_t *ps_pic_buf; 1681 UWORD8 i; 1682 UWORD32 u4_luma_size, u4_chroma_size; 1683 UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag; 1684 WORD32 j; 1685 UWORD8 *pu1_buf; 1686 1687 ps_pic_buf = ps_dec->ps_pic_buf_base; 1688 ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr); 1689 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr); 1690 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y; 1691 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv; 1692 1693 { 1694 if(ps_dec->u4_share_disp_buf == 1) 1695 { 1696 /* In case of buffers getting shared between application and library 1697 there is no need of reference memtabs. Instead of setting the i4_size 1698 to zero, it is reduced to a small i4_size to ensure that changes 1699 in the code are minimal */ 1700 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1701 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 1702 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 1703 { 1704 u4_luma_size = 64; 1705 } 1706 1707 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 1708 { 1709 u4_chroma_size = 64; 1710 } 1711 1712 } 1713 } 1714 1715 pu1_buf = ps_dec->pu1_pic_buf_base; 1716 1717 /* Allocate memory for refernce buffers */ 1718 for(i = 0; i < u1_num_of_buf; i++) 1719 { 1720 UWORD32 u4_offset; 1721 WORD32 buf_ret; 1722 UWORD8 *pu1_luma, *pu1_chroma; 1723 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1724 1725 pu1_luma = pu1_buf; 1726 pu1_buf += ALIGN64(u4_luma_size); 1727 pu1_chroma = pu1_buf; 1728 pu1_buf += ALIGN64(u4_chroma_size); 1729 1730 /* Offset to the start of the pic from the top left corner of the frame 1731 buffer */ 1732 1733 if((0 == ps_dec->u4_share_disp_buf) 1734 || (NULL == ps_dec->disp_bufs[i].buf[0])) 1735 { 1736 UWORD32 pad_len_h, pad_len_v; 1737 1738 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1739 ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset; 1740 1741 pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1)); 1742 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1743 1744 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1745 1746 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1747 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1748 1749 } 1750 else 1751 { 1752 UWORD32 pad_len_h, pad_len_v; 1753 u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H; 1754 ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0] 1755 + u4_offset; 1756 1757 ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset; 1758 1759 if(ps_dec->u1_chroma_format == IV_YUV_420P) 1760 { 1761 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 1762 (PAD_LEN_Y_H >> 1)); 1763 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1764 1765 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1766 ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset; 1767 ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset; 1768 1769 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 1770 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 1771 1772 } 1773 else 1774 { 1775 pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR, 1776 (PAD_LEN_Y_H >> 1)); 1777 pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V); 1778 1779 u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h; 1780 ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 1781 + u4_offset; 1782 ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1]) 1783 + u4_offset; 1784 1785 ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset; 1786 ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset; 1787 } 1788 } 1789 1790 ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y; 1791 ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv; 1792 ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y; 1793 ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv; 1794 1795 ps_pic_buf->u1_pic_buf_id = i; 1796 1797 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, 1798 ps_pic_buf, i); 1799 if(0 != buf_ret) 1800 { 1801 ps_dec->i4_error_code = ERROR_BUF_MGR; 1802 return ERROR_BUF_MGR; 1803 } 1804 1805 ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf; 1806 ps_pic_buf++; 1807 } 1808 1809 if(1 == ps_dec->u4_share_disp_buf) 1810 { 1811 for(i = 0; i < u1_num_of_buf; i++) 1812 ps_dec->u4_disp_buf_mapping[i] = 1; 1813 } 1814 return OK; 1815 } 1816 1817 /*! 1818 ************************************************************************** 1819 * \if Function name : ih264d_allocate_dynamic_bufs \endif 1820 * 1821 * \brief 1822 * This function allocates memory required by Decoder. 1823 * 1824 * \param ps_dec: Pointer to dec_struct_t. 1825 * 1826 * \return 1827 * Returns i4_status as returned by MemManager. 1828 * 1829 ************************************************************************** 1830 */ 1831 WORD16 ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec) 1832 { 1833 struct MemReq s_MemReq; 1834 struct MemBlock *p_MemBlock; 1835 1836 pred_info_t *ps_pred_frame; 1837 dec_mb_info_t *ps_frm_mb_info; 1838 dec_slice_struct_t *ps_dec_slice_buf; 1839 UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map; 1840 UWORD16 *pu2_slice_num_map; 1841 1842 WORD16 *pi16_res_coeff; 1843 WORD16 i16_status = 0; 1844 UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag); 1845 UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y; 1846 UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv; 1847 WORD8 c_i = 0; 1848 dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps; 1849 UWORD32 u4_total_mbs = ps_sps->u2_total_num_of_mbs << uc_frmOrFld; 1850 UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs; 1851 UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs; 1852 UWORD32 u4_blk_wd; 1853 UWORD32 ui_size = 0; 1854 UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0; 1855 UWORD8 *pu1_buf; 1856 WORD32 num_entries; 1857 WORD32 size; 1858 void *pv_buf; 1859 UWORD32 u4_num_bufs; 1860 UWORD32 u4_luma_size, u4_chroma_size; 1861 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 1862 1863 size = u4_total_mbs; 1864 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1865 RETURN_IF((NULL == pv_buf), IV_FAIL); 1866 ps_dec->pu1_dec_mb_map = pv_buf; 1867 1868 size = u4_total_mbs; 1869 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1870 RETURN_IF((NULL == pv_buf), IV_FAIL); 1871 ps_dec->pu1_recon_mb_map = pv_buf; 1872 1873 size = u4_total_mbs * sizeof(UWORD16); 1874 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1875 RETURN_IF((NULL == pv_buf), IV_FAIL); 1876 ps_dec->pu2_slice_num_map = pv_buf; 1877 1878 /************************************************************/ 1879 /* Post allocation Initialisations */ 1880 /************************************************************/ 1881 ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1882 ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1883 ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]); 1884 1885 ps_dec->ps_pred_start = ps_dec->ps_pred; 1886 1887 size = sizeof(parse_pmbarams_t) * (ps_dec->u1_recon_mb_grp); 1888 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1889 RETURN_IF((NULL == pv_buf), IV_FAIL); 1890 ps_dec->ps_parse_mb_data = pv_buf; 1891 1892 size = sizeof(parse_part_params_t) 1893 * ((ps_dec->u1_recon_mb_grp) << 4); 1894 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1895 RETURN_IF((NULL == pv_buf), IV_FAIL); 1896 ps_dec->ps_parse_part_params = pv_buf; 1897 1898 size = ((u4_wd_mbs * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld); 1899 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1900 RETURN_IF((NULL == pv_buf), IV_FAIL); 1901 ps_dec->ps_deblk_top_mb = pv_buf; 1902 1903 size = ((sizeof(ctxt_inc_mb_info_t)) 1904 * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1)); 1905 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1906 RETURN_IF((NULL == pv_buf), IV_FAIL); 1907 ps_dec->p_ctxt_inc_mb_map = pv_buf; 1908 1909 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 1910 * 16); 1911 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1912 RETURN_IF((NULL == pv_buf), IV_FAIL); 1913 ps_dec->ps_mv_p[0] = pv_buf; 1914 1915 size = (sizeof(mv_pred_t) * ps_dec->u1_recon_mb_grp 1916 * 16); 1917 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1918 RETURN_IF((NULL == pv_buf), IV_FAIL); 1919 ps_dec->ps_mv_p[1] = pv_buf; 1920 1921 { 1922 UWORD8 i; 1923 for(i = 0; i < MV_SCRATCH_BUFS; i++) 1924 { 1925 size = (sizeof(mv_pred_t) 1926 * ps_dec->u1_recon_mb_grp * 4); 1927 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1928 RETURN_IF((NULL == pv_buf), IV_FAIL); 1929 ps_dec->ps_mv_top_p[i] = pv_buf; 1930 } 1931 } 1932 1933 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1934 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1935 RETURN_IF((NULL == pv_buf), IV_FAIL); 1936 ps_dec->pu1_y_intra_pred_line = pv_buf; 1937 memset(ps_dec->pu1_y_intra_pred_line, 0, size); 1938 ps_dec->pu1_y_intra_pred_line += MB_SIZE; 1939 1940 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1941 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1942 RETURN_IF((NULL == pv_buf), IV_FAIL); 1943 ps_dec->pu1_u_intra_pred_line = pv_buf; 1944 memset(ps_dec->pu1_u_intra_pred_line, 0, size); 1945 ps_dec->pu1_u_intra_pred_line += MB_SIZE; 1946 1947 size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2; 1948 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1949 RETURN_IF((NULL == pv_buf), IV_FAIL); 1950 ps_dec->pu1_v_intra_pred_line = pv_buf; 1951 memset(ps_dec->pu1_v_intra_pred_line, 0, size); 1952 ps_dec->pu1_v_intra_pred_line += MB_SIZE; 1953 1954 if(ps_dec->u1_separate_parse) 1955 { 1956 size = sizeof(mb_neigbour_params_t) 1957 * 2 * ((u4_wd_mbs + 2) * u4_ht_mbs); 1958 } 1959 else 1960 { 1961 size = sizeof(mb_neigbour_params_t) 1962 * 2 * ((u4_wd_mbs + 2) << uc_frmOrFld); 1963 } 1964 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1965 RETURN_IF((NULL == pv_buf), IV_FAIL); 1966 1967 ps_dec->ps_nbr_mb_row = pv_buf; 1968 memset(ps_dec->ps_nbr_mb_row, 0, size); 1969 1970 /* Allocate deblock MB info */ 1971 size = (u4_total_mbs + u4_wd_mbs) * sizeof(deblk_mb_t); 1972 1973 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1974 RETURN_IF((NULL == pv_buf), IV_FAIL); 1975 ps_dec->ps_deblk_pic = pv_buf; 1976 1977 memset(ps_dec->ps_deblk_pic, 0, size); 1978 1979 /* Allocate frame level mb info */ 1980 size = sizeof(dec_mb_info_t) * u4_total_mbs; 1981 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 1982 RETURN_IF((NULL == pv_buf), IV_FAIL); 1983 ps_dec->ps_frm_mb_info = pv_buf; 1984 memset(ps_dec->ps_frm_mb_info, 0, size); 1985 1986 /* Allocate memory for slice headers dec_slice_struct_t */ 1987 num_entries = MAX_FRAMES; 1988 if((1 >= ps_dec->ps_cur_sps->u1_num_ref_frames) && 1989 (0 == ps_dec->i4_display_delay)) 1990 { 1991 num_entries = 1; 1992 } 1993 num_entries = ((2 * num_entries) + 1); 1994 if(BASE_PROFILE_IDC != ps_dec->ps_cur_sps->u1_profile_idc) 1995 { 1996 num_entries *= 2; 1997 } 1998 1999 size = num_entries * sizeof(void *); 2000 size += PAD_MAP_IDX_POC * sizeof(void *); 2001 size *= u4_total_mbs; 2002 size += sizeof(dec_slice_struct_t) * u4_total_mbs; 2003 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2004 RETURN_IF((NULL == pv_buf), IV_FAIL); 2005 2006 ps_dec->ps_dec_slice_buf = pv_buf; 2007 memset(ps_dec->ps_dec_slice_buf, 0, size); 2008 pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf; 2009 pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs; 2010 ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf; 2011 2012 /* Allocate memory for packed pred info */ 2013 num_entries = u4_total_mbs; 2014 if(1 == ps_dec->ps_cur_sps->u1_num_ref_frames) 2015 num_entries *= 16; 2016 else 2017 num_entries *= 16 * 2; 2018 2019 size = sizeof(pred_info_pkd_t) * num_entries; 2020 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2021 RETURN_IF((NULL == pv_buf), IV_FAIL); 2022 ps_dec->ps_pred_pkd = pv_buf; 2023 2024 /* Allocate memory for coeff data */ 2025 size = MB_LUM_SIZE * sizeof(WORD16); 2026 /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent 2027 For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent 2028 So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */ 2029 size += u4_total_mbs * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t)) 2030 + 9 * sizeof(tu_sblk4x4_coeff_data_t)); 2031 //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data 2032 size += u4_total_mbs * 32; 2033 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2034 RETURN_IF((NULL == pv_buf), IV_FAIL); 2035 2036 ps_dec->pi2_coeff_data = pv_buf; 2037 2038 ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE); 2039 2040 /* Allocate MV bank buffer */ 2041 { 2042 UWORD32 col_flag_buffer_size, mvpred_buffer_size; 2043 2044 col_flag_buffer_size = ((ps_dec->u2_pic_wd * ps_dec->u2_pic_ht) >> 4); 2045 mvpred_buffer_size = sizeof(mv_pred_t) 2046 * ((ps_dec->u2_pic_wd * (ps_dec->u2_pic_ht + PAD_MV_BANK_ROW)) >> 4); 2047 2048 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2049 2050 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs); 2051 u4_num_bufs = MAX(u4_num_bufs, 2); 2052 size = ALIGN64(mvpred_buffer_size) + ALIGN64(col_flag_buffer_size); 2053 size *= u4_num_bufs; 2054 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2055 RETURN_IF((NULL == pv_buf), IV_FAIL); 2056 ps_dec->pu1_mv_bank_buf_base = pv_buf; 2057 } 2058 2059 /* Allocate Pic buffer */ 2060 u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y; 2061 u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv; 2062 2063 { 2064 if(ps_dec->u4_share_disp_buf == 1) 2065 { 2066 /* In case of buffers getting shared between application and library 2067 there is no need of reference memtabs. Instead of setting the i4_size 2068 to zero, it is reduced to a small i4_size to ensure that changes 2069 in the code are minimal */ 2070 if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2071 || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU) 2072 || (ps_dec->u1_chroma_format == IV_YUV_420P)) 2073 { 2074 u4_luma_size = 64; 2075 } 2076 2077 if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV) 2078 { 2079 u4_chroma_size = 64; 2080 } 2081 2082 } 2083 } 2084 2085 size = ALIGN64(u4_luma_size) + ALIGN64(u4_chroma_size); 2086 size *= ps_dec->u1_pic_bufs; 2087 pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size); 2088 RETURN_IF((NULL == pv_buf), IV_FAIL); 2089 ps_dec->pu1_pic_buf_base = pv_buf; 2090 2091 /* 0th entry of CtxtIncMbMap will be always be containing default values 2092 for CABAC context representing MB not available */ 2093 ps_dec->p_ctxt_inc_mb_map += 1; 2094 /* Post allocation Increment Actions */ 2095 2096 /***************************************************************************/ 2097 /*Initialize cabac context pointers for every SE that has fixed contextIdx */ 2098 /***************************************************************************/ 2099 { 2100 bin_ctxt_model_t * const p_cabac_ctxt_table_t = 2101 ps_dec->p_cabac_ctxt_table_t; 2102 bin_ctxt_model_t * * p_coeff_abs_level_minus1_t = 2103 ps_dec->p_coeff_abs_level_minus1_t; 2104 bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t; 2105 2106 ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t 2107 + MB_FIELD_DECODING_FLAG; 2108 ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t 2109 + PREV_INTRA4X4_PRED_MODE_FLAG; 2110 ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t 2111 + REM_INTRA4X4_PRED_MODE; 2112 ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t 2113 + INTRA_CHROMA_PRED_MODE; 2114 ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA; 2115 ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX; 2116 ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X; 2117 ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y; 2118 p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0; 2119 p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4; 2120 p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8; 2121 p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12; 2122 p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16; 2123 ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA; 2124 ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA; 2125 2126 p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2127 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET; 2128 2129 p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2130 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET; 2131 2132 p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t 2133 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET; 2134 2135 p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t 2136 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET; 2137 2138 p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t 2139 + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET; 2140 2141 p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t 2142 + COEFF_ABS_LEVEL_MINUS1_8X8 2143 + COEFF_ABS_LEVEL_CAT_5_OFFSET; 2144 2145 /********************************************************/ 2146 /* context for the high profile related syntax elements */ 2147 /* This is maintained seperately in s_high_profile */ 2148 /********************************************************/ 2149 { 2150 2151 ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t 2152 + TRANSFORM_SIZE_8X8_FLAG; 2153 2154 ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t 2155 + SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2156 2157 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame = 2158 p_cabac_ctxt_table_t 2159 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME; 2160 2161 ps_dec->s_high_profile.ps_coeff_abs_levelminus1 = 2162 p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8; 2163 2164 ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t 2165 + SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2166 2167 ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field = 2168 p_cabac_ctxt_table_t 2169 + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD; 2170 } 2171 } 2172 return (i16_status); 2173 } 2174 2175 /*! 2176 ************************************************************************** 2177 * \if Function name : ih264d_free_dynamic_bufs \endif 2178 * 2179 * \brief 2180 * This function frees dynamic memory allocated by Decoder. 2181 * 2182 * \param ps_dec: Pointer to dec_struct_t. 2183 * 2184 * \return 2185 * Returns i4_status as returned by MemManager. 2186 * 2187 ************************************************************************** 2188 */ 2189 WORD16 ih264d_free_dynamic_bufs(dec_struct_t * ps_dec) 2190 { 2191 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic); 2192 2193 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_pic); 2194 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_dec_mb_map); 2195 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_recon_mb_map); 2196 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu2_slice_num_map); 2197 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_slice_buf); 2198 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_frm_mb_info); 2199 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_coeff_data); 2200 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_mb_data); 2201 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_part_params); 2202 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_top_mb); 2203 2204 if(ps_dec->p_ctxt_inc_mb_map) 2205 { 2206 ps_dec->p_ctxt_inc_mb_map -= 1; 2207 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_ctxt_inc_mb_map); 2208 } 2209 2210 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[0]); 2211 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[1]); 2212 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred_pkd); 2213 { 2214 UWORD8 i; 2215 for(i = 0; i < MV_SCRATCH_BUFS; i++) 2216 { 2217 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_top_p[i]); 2218 } 2219 } 2220 2221 if(ps_dec->pu1_y_intra_pred_line) 2222 { 2223 ps_dec->pu1_y_intra_pred_line -= MB_SIZE; 2224 } 2225 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_y_intra_pred_line); 2226 2227 if(ps_dec->pu1_u_intra_pred_line) 2228 { 2229 ps_dec->pu1_u_intra_pred_line -= MB_SIZE; 2230 } 2231 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_u_intra_pred_line); 2232 2233 if(ps_dec->pu1_v_intra_pred_line) 2234 { 2235 ps_dec->pu1_v_intra_pred_line -= MB_SIZE; 2236 } 2237 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_v_intra_pred_line); 2238 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_nbr_mb_row); 2239 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mv_bank_buf_base); 2240 PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_pic_buf_base); 2241 return 0; 2242 } 2243 2244 /*! 2245 ************************************************************************** 2246 * \if Function name : ih264d_create_mv_bank \endif 2247 * 2248 * \brief 2249 * This function creates MV bank. 2250 * 2251 * \param memType : Type of memory being handled 2252 * 0: Display Buffer 2253 * 1: Decoder Buffer 2254 * 2: Internal Buffer 2255 * \param u1_num_of_buf: Number of decode or display buffers. 2256 * \param u4_wd : Frame width. 2257 * \param u4_ht : Frame Height. 2258 * \param ps_pic_buf_api : Pointer to Picture Buffer API. 2259 * \param ih264d_dec_mem_manager : Memory manager utility supplied by system. 2260 * 2261 * \return 2262 * 0 on Success and -1 on error 2263 * 2264 ************************************************************************** 2265 */ 2266 WORD32 ih264d_create_mv_bank(void *pv_dec, 2267 UWORD32 ui_width, 2268 UWORD32 ui_height) 2269 { 2270 UWORD8 i; 2271 UWORD32 col_flag_buffer_size, mvpred_buffer_size; 2272 UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base; 2273 col_mv_buf_t *ps_col_mv; 2274 mv_pred_t *ps_mv; 2275 UWORD8 *pu1_col_zero_flag_buf; 2276 dec_struct_t *ps_dec = (dec_struct_t *)pv_dec; 2277 WORD32 buf_ret; 2278 UWORD32 u4_num_bufs; 2279 UWORD8 *pu1_buf; 2280 WORD32 size; 2281 void *pv_mem_ctxt = ps_dec->pv_mem_ctxt; 2282 2283 col_flag_buffer_size = ((ui_width * ui_height) >> 4); 2284 mvpred_buffer_size = sizeof(mv_pred_t) 2285 * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4); 2286 2287 ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr); 2288 2289 ps_col_mv = ps_dec->ps_col_mv_base; 2290 2291 u4_num_bufs = ps_dec->ps_cur_sps->u1_num_ref_frames + 1; 2292 2293 u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs); 2294 u4_num_bufs = MAX(u4_num_bufs, 2); 2295 pu1_buf = ps_dec->pu1_mv_bank_buf_base; 2296 for(i = 0 ; i < u4_num_bufs ; i++) 2297 { 2298 pu1_col_zero_flag_buf = pu1_buf; 2299 pu1_buf += ALIGN64(col_flag_buffer_size); 2300 2301 ps_mv = (mv_pred_t *)pu1_buf; 2302 pu1_buf += ALIGN64(mvpred_buffer_size); 2303 2304 memset(ps_mv, 0, ((ui_width * OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t)); 2305 ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4; 2306 2307 ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf; 2308 ps_col_mv->pv_mv = (void *)ps_mv; 2309 buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i); 2310 if(0 != buf_ret) 2311 { 2312 ps_dec->i4_error_code = ERROR_BUF_MGR; 2313 return ERROR_BUF_MGR; 2314 } 2315 ps_col_mv++; 2316 } 2317 return OK; 2318 } 2319 2320 void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4, 2321 WORD16 *pi2_out_coeff_data, 2322 UWORD8 *pu1_inv_scan) 2323 { 2324 UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map; 2325 WORD32 idx; 2326 WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0]; 2327 2328 while(u2_sig_coeff_map) 2329 { 2330 idx = CLZ(u2_sig_coeff_map); 2331 2332 idx = 31 - idx; 2333 RESET_BIT(u2_sig_coeff_map,idx); 2334 2335 idx = pu1_inv_scan[idx]; 2336 pi2_out_coeff_data[idx] = *pi2_coeff_data++; 2337 2338 } 2339 } 2340
