1 // Copyright 2013 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_ARM64_CONSTANTS_ARM64_H_ 6 #define V8_ARM64_CONSTANTS_ARM64_H_ 7 8 #include "src/base/macros.h" 9 #include "src/globals.h" 10 11 // Assert that this is an LP64 system. 12 STATIC_ASSERT(sizeof(int) == sizeof(int32_t)); 13 STATIC_ASSERT(sizeof(long) == sizeof(int64_t)); // NOLINT(runtime/int) 14 STATIC_ASSERT(sizeof(void *) == sizeof(int64_t)); 15 STATIC_ASSERT(sizeof(1) == sizeof(int32_t)); 16 STATIC_ASSERT(sizeof(1L) == sizeof(int64_t)); 17 18 19 // Get the standard printf format macros for C99 stdint types. 20 #ifndef __STDC_FORMAT_MACROS 21 #define __STDC_FORMAT_MACROS 22 #endif 23 #include <inttypes.h> 24 25 26 namespace v8 { 27 namespace internal { 28 29 30 const unsigned kInstructionSize = 4; 31 const unsigned kInstructionSizeLog2 = 2; 32 const unsigned kLoadLiteralScaleLog2 = 2; 33 const unsigned kMaxLoadLiteralRange = 1 * MB; 34 35 const int kNumberOfRegisters = 32; 36 const int kNumberOfFPRegisters = 32; 37 // Callee saved registers are x19-x30(lr). 38 const int kNumberOfCalleeSavedRegisters = 11; 39 const int kFirstCalleeSavedRegisterIndex = 19; 40 // Callee saved FP registers are d8-d15. 41 const int kNumberOfCalleeSavedFPRegisters = 8; 42 const int kFirstCalleeSavedFPRegisterIndex = 8; 43 // Callee saved registers with no specific purpose in JS are x19-x25. 44 const unsigned kJSCalleeSavedRegList = 0x03f80000; 45 const int kWRegSizeInBits = 32; 46 const int kWRegSizeInBitsLog2 = 5; 47 const int kWRegSize = kWRegSizeInBits >> 3; 48 const int kWRegSizeLog2 = kWRegSizeInBitsLog2 - 3; 49 const int kXRegSizeInBits = 64; 50 const int kXRegSizeInBitsLog2 = 6; 51 const int kXRegSize = kXRegSizeInBits >> 3; 52 const int kXRegSizeLog2 = kXRegSizeInBitsLog2 - 3; 53 const int kSRegSizeInBits = 32; 54 const int kSRegSizeInBitsLog2 = 5; 55 const int kSRegSize = kSRegSizeInBits >> 3; 56 const int kSRegSizeLog2 = kSRegSizeInBitsLog2 - 3; 57 const int kDRegSizeInBits = 64; 58 const int kDRegSizeInBitsLog2 = 6; 59 const int kDRegSize = kDRegSizeInBits >> 3; 60 const int kDRegSizeLog2 = kDRegSizeInBitsLog2 - 3; 61 const int64_t kWRegMask = 0x00000000ffffffffL; 62 const int64_t kXRegMask = 0xffffffffffffffffL; 63 const int64_t kSRegMask = 0x00000000ffffffffL; 64 const int64_t kDRegMask = 0xffffffffffffffffL; 65 // TODO(all) check if the expression below works on all compilers or if it 66 // triggers an overflow error. 67 const int64_t kDSignBit = 63; 68 const int64_t kDSignMask = 0x1L << kDSignBit; 69 const int64_t kSSignBit = 31; 70 const int64_t kSSignMask = 0x1L << kSSignBit; 71 const int64_t kXSignBit = 63; 72 const int64_t kXSignMask = 0x1L << kXSignBit; 73 const int64_t kWSignBit = 31; 74 const int64_t kWSignMask = 0x1L << kWSignBit; 75 const int64_t kDQuietNanBit = 51; 76 const int64_t kDQuietNanMask = 0x1L << kDQuietNanBit; 77 const int64_t kSQuietNanBit = 22; 78 const int64_t kSQuietNanMask = 0x1L << kSQuietNanBit; 79 const int64_t kByteMask = 0xffL; 80 const int64_t kHalfWordMask = 0xffffL; 81 const int64_t kWordMask = 0xffffffffL; 82 const uint64_t kXMaxUInt = 0xffffffffffffffffUL; 83 const uint64_t kWMaxUInt = 0xffffffffUL; 84 const int64_t kXMaxInt = 0x7fffffffffffffffL; 85 const int64_t kXMinInt = 0x8000000000000000L; 86 const int32_t kWMaxInt = 0x7fffffff; 87 const int32_t kWMinInt = 0x80000000; 88 const int kIp0Code = 16; 89 const int kIp1Code = 17; 90 const int kFramePointerRegCode = 29; 91 const int kLinkRegCode = 30; 92 const int kZeroRegCode = 31; 93 const int kJSSPCode = 28; 94 const int kSPRegInternalCode = 63; 95 const unsigned kRegCodeMask = 0x1f; 96 const unsigned kShiftAmountWRegMask = 0x1f; 97 const unsigned kShiftAmountXRegMask = 0x3f; 98 // Standard machine types defined by AAPCS64. 99 const unsigned kByteSize = 8; 100 const unsigned kByteSizeInBytes = kByteSize >> 3; 101 const unsigned kHalfWordSize = 16; 102 const unsigned kHalfWordSizeLog2 = 4; 103 const unsigned kHalfWordSizeInBytes = kHalfWordSize >> 3; 104 const unsigned kHalfWordSizeInBytesLog2 = kHalfWordSizeLog2 - 3; 105 const unsigned kWordSize = 32; 106 const unsigned kWordSizeLog2 = 5; 107 const unsigned kWordSizeInBytes = kWordSize >> 3; 108 const unsigned kWordSizeInBytesLog2 = kWordSizeLog2 - 3; 109 const unsigned kDoubleWordSize = 64; 110 const unsigned kDoubleWordSizeInBytes = kDoubleWordSize >> 3; 111 const unsigned kQuadWordSize = 128; 112 const unsigned kQuadWordSizeInBytes = kQuadWordSize >> 3; 113 // AArch64 floating-point specifics. These match IEEE-754. 114 const unsigned kDoubleMantissaBits = 52; 115 const unsigned kDoubleExponentBits = 11; 116 const unsigned kDoubleExponentBias = 1023; 117 const unsigned kFloatMantissaBits = 23; 118 const unsigned kFloatExponentBits = 8; 119 120 #define INSTRUCTION_FIELDS_LIST(V_) \ 121 /* Register fields */ \ 122 V_(Rd, 4, 0, Bits) /* Destination register. */ \ 123 V_(Rn, 9, 5, Bits) /* First source register. */ \ 124 V_(Rm, 20, 16, Bits) /* Second source register. */ \ 125 V_(Ra, 14, 10, Bits) /* Third source register. */ \ 126 V_(Rt, 4, 0, Bits) /* Load dest / store source. */ \ 127 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \ 128 /* store second source. */ \ 129 V_(PrefetchMode, 4, 0, Bits) \ 130 \ 131 /* Common bits */ \ 132 V_(SixtyFourBits, 31, 31, Bits) \ 133 V_(FlagsUpdate, 29, 29, Bits) \ 134 \ 135 /* PC relative addressing */ \ 136 V_(ImmPCRelHi, 23, 5, SignedBits) \ 137 V_(ImmPCRelLo, 30, 29, Bits) \ 138 \ 139 /* Add/subtract/logical shift register */ \ 140 V_(ShiftDP, 23, 22, Bits) \ 141 V_(ImmDPShift, 15, 10, Bits) \ 142 \ 143 /* Add/subtract immediate */ \ 144 V_(ImmAddSub, 21, 10, Bits) \ 145 V_(ShiftAddSub, 23, 22, Bits) \ 146 \ 147 /* Add/substract extend */ \ 148 V_(ImmExtendShift, 12, 10, Bits) \ 149 V_(ExtendMode, 15, 13, Bits) \ 150 \ 151 /* Move wide */ \ 152 V_(ImmMoveWide, 20, 5, Bits) \ 153 V_(ShiftMoveWide, 22, 21, Bits) \ 154 \ 155 /* Logical immediate, bitfield and extract */ \ 156 V_(BitN, 22, 22, Bits) \ 157 V_(ImmRotate, 21, 16, Bits) \ 158 V_(ImmSetBits, 15, 10, Bits) \ 159 V_(ImmR, 21, 16, Bits) \ 160 V_(ImmS, 15, 10, Bits) \ 161 \ 162 /* Test and branch immediate */ \ 163 V_(ImmTestBranch, 18, 5, SignedBits) \ 164 V_(ImmTestBranchBit40, 23, 19, Bits) \ 165 V_(ImmTestBranchBit5, 31, 31, Bits) \ 166 \ 167 /* Conditionals */ \ 168 V_(Condition, 15, 12, Bits) \ 169 V_(ConditionBranch, 3, 0, Bits) \ 170 V_(Nzcv, 3, 0, Bits) \ 171 V_(ImmCondCmp, 20, 16, Bits) \ 172 V_(ImmCondBranch, 23, 5, SignedBits) \ 173 \ 174 /* Floating point */ \ 175 V_(FPType, 23, 22, Bits) \ 176 V_(ImmFP, 20, 13, Bits) \ 177 V_(FPScale, 15, 10, Bits) \ 178 \ 179 /* Load Store */ \ 180 V_(ImmLS, 20, 12, SignedBits) \ 181 V_(ImmLSUnsigned, 21, 10, Bits) \ 182 V_(ImmLSPair, 21, 15, SignedBits) \ 183 V_(SizeLS, 31, 30, Bits) \ 184 V_(ImmShiftLS, 12, 12, Bits) \ 185 \ 186 /* Other immediates */ \ 187 V_(ImmUncondBranch, 25, 0, SignedBits) \ 188 V_(ImmCmpBranch, 23, 5, SignedBits) \ 189 V_(ImmLLiteral, 23, 5, SignedBits) \ 190 V_(ImmException, 20, 5, Bits) \ 191 V_(ImmHint, 11, 5, Bits) \ 192 V_(ImmBarrierDomain, 11, 10, Bits) \ 193 V_(ImmBarrierType, 9, 8, Bits) \ 194 \ 195 /* System (MRS, MSR) */ \ 196 V_(ImmSystemRegister, 19, 5, Bits) \ 197 V_(SysO0, 19, 19, Bits) \ 198 V_(SysOp1, 18, 16, Bits) \ 199 V_(SysOp2, 7, 5, Bits) \ 200 V_(CRn, 15, 12, Bits) \ 201 V_(CRm, 11, 8, Bits) \ 202 203 204 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 205 /* NZCV */ \ 206 V_(Flags, 31, 28, Bits, uint32_t) \ 207 V_(N, 31, 31, Bits, bool) \ 208 V_(Z, 30, 30, Bits, bool) \ 209 V_(C, 29, 29, Bits, bool) \ 210 V_(V, 28, 28, Bits, uint32_t) \ 211 M_(NZCV, Flags_mask) \ 212 \ 213 /* FPCR */ \ 214 V_(AHP, 26, 26, Bits, bool) \ 215 V_(DN, 25, 25, Bits, bool) \ 216 V_(FZ, 24, 24, Bits, bool) \ 217 V_(RMode, 23, 22, Bits, FPRounding) \ 218 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 219 220 221 // Fields offsets. 222 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) \ 223 const int Name##_offset = LowBit; \ 224 const int Name##_width = HighBit - LowBit + 1; \ 225 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; 226 #define DECLARE_INSTRUCTION_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1) \ 227 DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, unused_1, unused_2) 228 #define NOTHING(A, B) 229 INSTRUCTION_FIELDS_LIST(DECLARE_INSTRUCTION_FIELDS_OFFSETS) 230 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) 231 #undef NOTHING 232 #undef DECLARE_FIELDS_OFFSETS 233 #undef DECLARE_INSTRUCTION_FIELDS_OFFSETS 234 235 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed 236 // from ImmPCRelLo and ImmPCRelHi. 237 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; 238 239 // Condition codes. 240 enum Condition { 241 eq = 0, 242 ne = 1, 243 hs = 2, cs = hs, 244 lo = 3, cc = lo, 245 mi = 4, 246 pl = 5, 247 vs = 6, 248 vc = 7, 249 hi = 8, 250 ls = 9, 251 ge = 10, 252 lt = 11, 253 gt = 12, 254 le = 13, 255 al = 14, 256 nv = 15 // Behaves as always/al. 257 }; 258 259 inline Condition NegateCondition(Condition cond) { 260 // Conditions al and nv behave identically, as "always true". They can't be 261 // inverted, because there is no never condition. 262 DCHECK((cond != al) && (cond != nv)); 263 return static_cast<Condition>(cond ^ 1); 264 } 265 266 // Commute a condition such that {a cond b == b cond' a}. 267 inline Condition CommuteCondition(Condition cond) { 268 switch (cond) { 269 case lo: 270 return hi; 271 case hi: 272 return lo; 273 case hs: 274 return ls; 275 case ls: 276 return hs; 277 case lt: 278 return gt; 279 case gt: 280 return lt; 281 case ge: 282 return le; 283 case le: 284 return ge; 285 case eq: 286 return eq; 287 default: 288 // In practice this function is only used with a condition coming from 289 // TokenToCondition in lithium-codegen-arm64.cc. Any other condition is 290 // invalid as it doesn't necessary make sense to reverse it (consider 291 // 'mi' for instance). 292 UNREACHABLE(); 293 return nv; 294 } 295 } 296 297 enum FlagsUpdate { 298 SetFlags = 1, 299 LeaveFlags = 0 300 }; 301 302 enum StatusFlags { 303 NoFlag = 0, 304 305 // Derive the flag combinations from the system register bit descriptions. 306 NFlag = N_mask, 307 ZFlag = Z_mask, 308 CFlag = C_mask, 309 VFlag = V_mask, 310 NZFlag = NFlag | ZFlag, 311 NCFlag = NFlag | CFlag, 312 NVFlag = NFlag | VFlag, 313 ZCFlag = ZFlag | CFlag, 314 ZVFlag = ZFlag | VFlag, 315 CVFlag = CFlag | VFlag, 316 NZCFlag = NFlag | ZFlag | CFlag, 317 NZVFlag = NFlag | ZFlag | VFlag, 318 NCVFlag = NFlag | CFlag | VFlag, 319 ZCVFlag = ZFlag | CFlag | VFlag, 320 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, 321 322 // Floating-point comparison results. 323 FPEqualFlag = ZCFlag, 324 FPLessThanFlag = NFlag, 325 FPGreaterThanFlag = CFlag, 326 FPUnorderedFlag = CVFlag 327 }; 328 329 enum Shift { 330 NO_SHIFT = -1, 331 LSL = 0x0, 332 LSR = 0x1, 333 ASR = 0x2, 334 ROR = 0x3 335 }; 336 337 enum Extend { 338 NO_EXTEND = -1, 339 UXTB = 0, 340 UXTH = 1, 341 UXTW = 2, 342 UXTX = 3, 343 SXTB = 4, 344 SXTH = 5, 345 SXTW = 6, 346 SXTX = 7 347 }; 348 349 enum SystemHint { 350 NOP = 0, 351 YIELD = 1, 352 WFE = 2, 353 WFI = 3, 354 SEV = 4, 355 SEVL = 5 356 }; 357 358 enum BarrierDomain { 359 OuterShareable = 0, 360 NonShareable = 1, 361 InnerShareable = 2, 362 FullSystem = 3 363 }; 364 365 enum BarrierType { 366 BarrierOther = 0, 367 BarrierReads = 1, 368 BarrierWrites = 2, 369 BarrierAll = 3 370 }; 371 372 // System/special register names. 373 // This information is not encoded as one field but as the concatenation of 374 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2). 375 enum SystemRegister { 376 NZCV = ((0x1 << SysO0_offset) | 377 (0x3 << SysOp1_offset) | 378 (0x4 << CRn_offset) | 379 (0x2 << CRm_offset) | 380 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset, 381 FPCR = ((0x1 << SysO0_offset) | 382 (0x3 << SysOp1_offset) | 383 (0x4 << CRn_offset) | 384 (0x4 << CRm_offset) | 385 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset 386 }; 387 388 // Instruction enumerations. 389 // 390 // These are the masks that define a class of instructions, and the list of 391 // instructions within each class. Each enumeration has a Fixed, FMask and 392 // Mask value. 393 // 394 // Fixed: The fixed bits in this instruction class. 395 // FMask: The mask used to extract the fixed bits in the class. 396 // Mask: The mask used to identify the instructions within a class. 397 // 398 // The enumerations can be used like this: 399 // 400 // DCHECK(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); 401 // switch(instr->Mask(PCRelAddressingMask)) { 402 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; 403 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; 404 // default: printf("Unknown instruction\n"); 405 // } 406 407 408 // Generic fields. 409 enum GenericInstrField { 410 SixtyFourBits = 0x80000000, 411 ThirtyTwoBits = 0x00000000, 412 FP32 = 0x00000000, 413 FP64 = 0x00400000 414 }; 415 416 // PC relative addressing. 417 enum PCRelAddressingOp { 418 PCRelAddressingFixed = 0x10000000, 419 PCRelAddressingFMask = 0x1F000000, 420 PCRelAddressingMask = 0x9F000000, 421 ADR = PCRelAddressingFixed | 0x00000000, 422 ADRP = PCRelAddressingFixed | 0x80000000 423 }; 424 425 // Add/sub (immediate, shifted and extended.) 426 const int kSFOffset = 31; 427 enum AddSubOp { 428 AddSubOpMask = 0x60000000, 429 AddSubSetFlagsBit = 0x20000000, 430 ADD = 0x00000000, 431 ADDS = ADD | AddSubSetFlagsBit, 432 SUB = 0x40000000, 433 SUBS = SUB | AddSubSetFlagsBit 434 }; 435 436 #define ADD_SUB_OP_LIST(V) \ 437 V(ADD), \ 438 V(ADDS), \ 439 V(SUB), \ 440 V(SUBS) 441 442 enum AddSubImmediateOp { 443 AddSubImmediateFixed = 0x11000000, 444 AddSubImmediateFMask = 0x1F000000, 445 AddSubImmediateMask = 0xFF000000, 446 #define ADD_SUB_IMMEDIATE(A) \ 447 A##_w_imm = AddSubImmediateFixed | A, \ 448 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits 449 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) 450 #undef ADD_SUB_IMMEDIATE 451 }; 452 453 enum AddSubShiftedOp { 454 AddSubShiftedFixed = 0x0B000000, 455 AddSubShiftedFMask = 0x1F200000, 456 AddSubShiftedMask = 0xFF200000, 457 #define ADD_SUB_SHIFTED(A) \ 458 A##_w_shift = AddSubShiftedFixed | A, \ 459 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits 460 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) 461 #undef ADD_SUB_SHIFTED 462 }; 463 464 enum AddSubExtendedOp { 465 AddSubExtendedFixed = 0x0B200000, 466 AddSubExtendedFMask = 0x1F200000, 467 AddSubExtendedMask = 0xFFE00000, 468 #define ADD_SUB_EXTENDED(A) \ 469 A##_w_ext = AddSubExtendedFixed | A, \ 470 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits 471 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) 472 #undef ADD_SUB_EXTENDED 473 }; 474 475 // Add/sub with carry. 476 enum AddSubWithCarryOp { 477 AddSubWithCarryFixed = 0x1A000000, 478 AddSubWithCarryFMask = 0x1FE00000, 479 AddSubWithCarryMask = 0xFFE0FC00, 480 ADC_w = AddSubWithCarryFixed | ADD, 481 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, 482 ADC = ADC_w, 483 ADCS_w = AddSubWithCarryFixed | ADDS, 484 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, 485 SBC_w = AddSubWithCarryFixed | SUB, 486 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, 487 SBC = SBC_w, 488 SBCS_w = AddSubWithCarryFixed | SUBS, 489 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits 490 }; 491 492 493 // Logical (immediate and shifted register). 494 enum LogicalOp { 495 LogicalOpMask = 0x60200000, 496 NOT = 0x00200000, 497 AND = 0x00000000, 498 BIC = AND | NOT, 499 ORR = 0x20000000, 500 ORN = ORR | NOT, 501 EOR = 0x40000000, 502 EON = EOR | NOT, 503 ANDS = 0x60000000, 504 BICS = ANDS | NOT 505 }; 506 507 // Logical immediate. 508 enum LogicalImmediateOp { 509 LogicalImmediateFixed = 0x12000000, 510 LogicalImmediateFMask = 0x1F800000, 511 LogicalImmediateMask = 0xFF800000, 512 AND_w_imm = LogicalImmediateFixed | AND, 513 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, 514 ORR_w_imm = LogicalImmediateFixed | ORR, 515 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, 516 EOR_w_imm = LogicalImmediateFixed | EOR, 517 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, 518 ANDS_w_imm = LogicalImmediateFixed | ANDS, 519 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 520 }; 521 522 // Logical shifted register. 523 enum LogicalShiftedOp { 524 LogicalShiftedFixed = 0x0A000000, 525 LogicalShiftedFMask = 0x1F000000, 526 LogicalShiftedMask = 0xFF200000, 527 AND_w = LogicalShiftedFixed | AND, 528 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, 529 AND_shift = AND_w, 530 BIC_w = LogicalShiftedFixed | BIC, 531 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, 532 BIC_shift = BIC_w, 533 ORR_w = LogicalShiftedFixed | ORR, 534 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, 535 ORR_shift = ORR_w, 536 ORN_w = LogicalShiftedFixed | ORN, 537 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, 538 ORN_shift = ORN_w, 539 EOR_w = LogicalShiftedFixed | EOR, 540 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, 541 EOR_shift = EOR_w, 542 EON_w = LogicalShiftedFixed | EON, 543 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, 544 EON_shift = EON_w, 545 ANDS_w = LogicalShiftedFixed | ANDS, 546 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, 547 ANDS_shift = ANDS_w, 548 BICS_w = LogicalShiftedFixed | BICS, 549 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, 550 BICS_shift = BICS_w 551 }; 552 553 // Move wide immediate. 554 enum MoveWideImmediateOp { 555 MoveWideImmediateFixed = 0x12800000, 556 MoveWideImmediateFMask = 0x1F800000, 557 MoveWideImmediateMask = 0xFF800000, 558 MOVN = 0x00000000, 559 MOVZ = 0x40000000, 560 MOVK = 0x60000000, 561 MOVN_w = MoveWideImmediateFixed | MOVN, 562 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, 563 MOVZ_w = MoveWideImmediateFixed | MOVZ, 564 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, 565 MOVK_w = MoveWideImmediateFixed | MOVK, 566 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits 567 }; 568 569 // Bitfield. 570 const int kBitfieldNOffset = 22; 571 enum BitfieldOp { 572 BitfieldFixed = 0x13000000, 573 BitfieldFMask = 0x1F800000, 574 BitfieldMask = 0xFF800000, 575 SBFM_w = BitfieldFixed | 0x00000000, 576 SBFM_x = BitfieldFixed | 0x80000000, 577 SBFM = SBFM_w, 578 BFM_w = BitfieldFixed | 0x20000000, 579 BFM_x = BitfieldFixed | 0xA0000000, 580 BFM = BFM_w, 581 UBFM_w = BitfieldFixed | 0x40000000, 582 UBFM_x = BitfieldFixed | 0xC0000000, 583 UBFM = UBFM_w 584 // Bitfield N field. 585 }; 586 587 // Extract. 588 enum ExtractOp { 589 ExtractFixed = 0x13800000, 590 ExtractFMask = 0x1F800000, 591 ExtractMask = 0xFFA00000, 592 EXTR_w = ExtractFixed | 0x00000000, 593 EXTR_x = ExtractFixed | 0x80000000, 594 EXTR = EXTR_w 595 }; 596 597 // Unconditional branch. 598 enum UnconditionalBranchOp { 599 UnconditionalBranchFixed = 0x14000000, 600 UnconditionalBranchFMask = 0x7C000000, 601 UnconditionalBranchMask = 0xFC000000, 602 B = UnconditionalBranchFixed | 0x00000000, 603 BL = UnconditionalBranchFixed | 0x80000000 604 }; 605 606 // Unconditional branch to register. 607 enum UnconditionalBranchToRegisterOp { 608 UnconditionalBranchToRegisterFixed = 0xD6000000, 609 UnconditionalBranchToRegisterFMask = 0xFE000000, 610 UnconditionalBranchToRegisterMask = 0xFFFFFC1F, 611 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, 612 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, 613 RET = UnconditionalBranchToRegisterFixed | 0x005F0000 614 }; 615 616 // Compare and branch. 617 enum CompareBranchOp { 618 CompareBranchFixed = 0x34000000, 619 CompareBranchFMask = 0x7E000000, 620 CompareBranchMask = 0xFF000000, 621 CBZ_w = CompareBranchFixed | 0x00000000, 622 CBZ_x = CompareBranchFixed | 0x80000000, 623 CBZ = CBZ_w, 624 CBNZ_w = CompareBranchFixed | 0x01000000, 625 CBNZ_x = CompareBranchFixed | 0x81000000, 626 CBNZ = CBNZ_w 627 }; 628 629 // Test and branch. 630 enum TestBranchOp { 631 TestBranchFixed = 0x36000000, 632 TestBranchFMask = 0x7E000000, 633 TestBranchMask = 0x7F000000, 634 TBZ = TestBranchFixed | 0x00000000, 635 TBNZ = TestBranchFixed | 0x01000000 636 }; 637 638 // Conditional branch. 639 enum ConditionalBranchOp { 640 ConditionalBranchFixed = 0x54000000, 641 ConditionalBranchFMask = 0xFE000000, 642 ConditionalBranchMask = 0xFF000010, 643 B_cond = ConditionalBranchFixed | 0x00000000 644 }; 645 646 // System. 647 // System instruction encoding is complicated because some instructions use op 648 // and CR fields to encode parameters. To handle this cleanly, the system 649 // instructions are split into more than one enum. 650 651 enum SystemOp { 652 SystemFixed = 0xD5000000, 653 SystemFMask = 0xFFC00000 654 }; 655 656 enum SystemSysRegOp { 657 SystemSysRegFixed = 0xD5100000, 658 SystemSysRegFMask = 0xFFD00000, 659 SystemSysRegMask = 0xFFF00000, 660 MRS = SystemSysRegFixed | 0x00200000, 661 MSR = SystemSysRegFixed | 0x00000000 662 }; 663 664 enum SystemHintOp { 665 SystemHintFixed = 0xD503201F, 666 SystemHintFMask = 0xFFFFF01F, 667 SystemHintMask = 0xFFFFF01F, 668 HINT = SystemHintFixed | 0x00000000 669 }; 670 671 // Exception. 672 enum ExceptionOp { 673 ExceptionFixed = 0xD4000000, 674 ExceptionFMask = 0xFF000000, 675 ExceptionMask = 0xFFE0001F, 676 HLT = ExceptionFixed | 0x00400000, 677 BRK = ExceptionFixed | 0x00200000, 678 SVC = ExceptionFixed | 0x00000001, 679 HVC = ExceptionFixed | 0x00000002, 680 SMC = ExceptionFixed | 0x00000003, 681 DCPS1 = ExceptionFixed | 0x00A00001, 682 DCPS2 = ExceptionFixed | 0x00A00002, 683 DCPS3 = ExceptionFixed | 0x00A00003 684 }; 685 // Code used to spot hlt instructions that should not be hit. 686 const int kHltBadCode = 0xbad; 687 688 enum MemBarrierOp { 689 MemBarrierFixed = 0xD503309F, 690 MemBarrierFMask = 0xFFFFF09F, 691 MemBarrierMask = 0xFFFFF0FF, 692 DSB = MemBarrierFixed | 0x00000000, 693 DMB = MemBarrierFixed | 0x00000020, 694 ISB = MemBarrierFixed | 0x00000040 695 }; 696 697 // Any load or store (including pair). 698 enum LoadStoreAnyOp { 699 LoadStoreAnyFMask = 0x0a000000, 700 LoadStoreAnyFixed = 0x08000000 701 }; 702 703 // Any load pair or store pair. 704 enum LoadStorePairAnyOp { 705 LoadStorePairAnyFMask = 0x3a000000, 706 LoadStorePairAnyFixed = 0x28000000 707 }; 708 709 #define LOAD_STORE_PAIR_OP_LIST(V) \ 710 V(STP, w, 0x00000000), \ 711 V(LDP, w, 0x00400000), \ 712 V(LDPSW, x, 0x40400000), \ 713 V(STP, x, 0x80000000), \ 714 V(LDP, x, 0x80400000), \ 715 V(STP, s, 0x04000000), \ 716 V(LDP, s, 0x04400000), \ 717 V(STP, d, 0x44000000), \ 718 V(LDP, d, 0x44400000) 719 720 // Load/store pair (post, pre and offset.) 721 enum LoadStorePairOp { 722 LoadStorePairMask = 0xC4400000, 723 LoadStorePairLBit = 1 << 22, 724 #define LOAD_STORE_PAIR(A, B, C) \ 725 A##_##B = C 726 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 727 #undef LOAD_STORE_PAIR 728 }; 729 730 enum LoadStorePairPostIndexOp { 731 LoadStorePairPostIndexFixed = 0x28800000, 732 LoadStorePairPostIndexFMask = 0x3B800000, 733 LoadStorePairPostIndexMask = 0xFFC00000, 734 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ 735 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B 736 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) 737 #undef LOAD_STORE_PAIR_POST_INDEX 738 }; 739 740 enum LoadStorePairPreIndexOp { 741 LoadStorePairPreIndexFixed = 0x29800000, 742 LoadStorePairPreIndexFMask = 0x3B800000, 743 LoadStorePairPreIndexMask = 0xFFC00000, 744 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ 745 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B 746 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) 747 #undef LOAD_STORE_PAIR_PRE_INDEX 748 }; 749 750 enum LoadStorePairOffsetOp { 751 LoadStorePairOffsetFixed = 0x29000000, 752 LoadStorePairOffsetFMask = 0x3B800000, 753 LoadStorePairOffsetMask = 0xFFC00000, 754 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ 755 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B 756 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) 757 #undef LOAD_STORE_PAIR_OFFSET 758 }; 759 760 // Load literal. 761 enum LoadLiteralOp { 762 LoadLiteralFixed = 0x18000000, 763 LoadLiteralFMask = 0x3B000000, 764 LoadLiteralMask = 0xFF000000, 765 LDR_w_lit = LoadLiteralFixed | 0x00000000, 766 LDR_x_lit = LoadLiteralFixed | 0x40000000, 767 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 768 PRFM_lit = LoadLiteralFixed | 0xC0000000, 769 LDR_s_lit = LoadLiteralFixed | 0x04000000, 770 LDR_d_lit = LoadLiteralFixed | 0x44000000 771 }; 772 773 #define LOAD_STORE_OP_LIST(V) \ 774 V(ST, RB, w, 0x00000000), \ 775 V(ST, RH, w, 0x40000000), \ 776 V(ST, R, w, 0x80000000), \ 777 V(ST, R, x, 0xC0000000), \ 778 V(LD, RB, w, 0x00400000), \ 779 V(LD, RH, w, 0x40400000), \ 780 V(LD, R, w, 0x80400000), \ 781 V(LD, R, x, 0xC0400000), \ 782 V(LD, RSB, x, 0x00800000), \ 783 V(LD, RSH, x, 0x40800000), \ 784 V(LD, RSW, x, 0x80800000), \ 785 V(LD, RSB, w, 0x00C00000), \ 786 V(LD, RSH, w, 0x40C00000), \ 787 V(ST, R, s, 0x84000000), \ 788 V(ST, R, d, 0xC4000000), \ 789 V(LD, R, s, 0x84400000), \ 790 V(LD, R, d, 0xC4400000) 791 792 793 // Load/store unscaled offset. 794 enum LoadStoreUnscaledOffsetOp { 795 LoadStoreUnscaledOffsetFixed = 0x38000000, 796 LoadStoreUnscaledOffsetFMask = 0x3B200C00, 797 LoadStoreUnscaledOffsetMask = 0xFFE00C00, 798 #define LOAD_STORE_UNSCALED(A, B, C, D) \ 799 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 800 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 801 #undef LOAD_STORE_UNSCALED 802 }; 803 804 // Load/store (post, pre, offset and unsigned.) 805 enum LoadStoreOp { 806 LoadStoreOpMask = 0xC4C00000, 807 #define LOAD_STORE(A, B, C, D) \ 808 A##B##_##C = D 809 LOAD_STORE_OP_LIST(LOAD_STORE), 810 #undef LOAD_STORE 811 PRFM = 0xC0800000 812 }; 813 814 // Load/store post index. 815 enum LoadStorePostIndex { 816 LoadStorePostIndexFixed = 0x38000400, 817 LoadStorePostIndexFMask = 0x3B200C00, 818 LoadStorePostIndexMask = 0xFFE00C00, 819 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 820 A##B##_##C##_post = LoadStorePostIndexFixed | D 821 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) 822 #undef LOAD_STORE_POST_INDEX 823 }; 824 825 // Load/store pre index. 826 enum LoadStorePreIndex { 827 LoadStorePreIndexFixed = 0x38000C00, 828 LoadStorePreIndexFMask = 0x3B200C00, 829 LoadStorePreIndexMask = 0xFFE00C00, 830 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ 831 A##B##_##C##_pre = LoadStorePreIndexFixed | D 832 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) 833 #undef LOAD_STORE_PRE_INDEX 834 }; 835 836 // Load/store unsigned offset. 837 enum LoadStoreUnsignedOffset { 838 LoadStoreUnsignedOffsetFixed = 0x39000000, 839 LoadStoreUnsignedOffsetFMask = 0x3B000000, 840 LoadStoreUnsignedOffsetMask = 0xFFC00000, 841 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, 842 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ 843 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D 844 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) 845 #undef LOAD_STORE_UNSIGNED_OFFSET 846 }; 847 848 // Load/store register offset. 849 enum LoadStoreRegisterOffset { 850 LoadStoreRegisterOffsetFixed = 0x38200800, 851 LoadStoreRegisterOffsetFMask = 0x3B200C00, 852 LoadStoreRegisterOffsetMask = 0xFFE00C00, 853 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 854 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 855 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 856 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 857 #undef LOAD_STORE_REGISTER_OFFSET 858 }; 859 860 // Conditional compare. 861 enum ConditionalCompareOp { 862 ConditionalCompareMask = 0x60000000, 863 CCMN = 0x20000000, 864 CCMP = 0x60000000 865 }; 866 867 // Conditional compare register. 868 enum ConditionalCompareRegisterOp { 869 ConditionalCompareRegisterFixed = 0x1A400000, 870 ConditionalCompareRegisterFMask = 0x1FE00800, 871 ConditionalCompareRegisterMask = 0xFFE00C10, 872 CCMN_w = ConditionalCompareRegisterFixed | CCMN, 873 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, 874 CCMP_w = ConditionalCompareRegisterFixed | CCMP, 875 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP 876 }; 877 878 // Conditional compare immediate. 879 enum ConditionalCompareImmediateOp { 880 ConditionalCompareImmediateFixed = 0x1A400800, 881 ConditionalCompareImmediateFMask = 0x1FE00800, 882 ConditionalCompareImmediateMask = 0xFFE00C10, 883 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, 884 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, 885 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, 886 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP 887 }; 888 889 // Conditional select. 890 enum ConditionalSelectOp { 891 ConditionalSelectFixed = 0x1A800000, 892 ConditionalSelectFMask = 0x1FE00000, 893 ConditionalSelectMask = 0xFFE00C00, 894 CSEL_w = ConditionalSelectFixed | 0x00000000, 895 CSEL_x = ConditionalSelectFixed | 0x80000000, 896 CSEL = CSEL_w, 897 CSINC_w = ConditionalSelectFixed | 0x00000400, 898 CSINC_x = ConditionalSelectFixed | 0x80000400, 899 CSINC = CSINC_w, 900 CSINV_w = ConditionalSelectFixed | 0x40000000, 901 CSINV_x = ConditionalSelectFixed | 0xC0000000, 902 CSINV = CSINV_w, 903 CSNEG_w = ConditionalSelectFixed | 0x40000400, 904 CSNEG_x = ConditionalSelectFixed | 0xC0000400, 905 CSNEG = CSNEG_w 906 }; 907 908 // Data processing 1 source. 909 enum DataProcessing1SourceOp { 910 DataProcessing1SourceFixed = 0x5AC00000, 911 DataProcessing1SourceFMask = 0x5FE00000, 912 DataProcessing1SourceMask = 0xFFFFFC00, 913 RBIT = DataProcessing1SourceFixed | 0x00000000, 914 RBIT_w = RBIT, 915 RBIT_x = RBIT | SixtyFourBits, 916 REV16 = DataProcessing1SourceFixed | 0x00000400, 917 REV16_w = REV16, 918 REV16_x = REV16 | SixtyFourBits, 919 REV = DataProcessing1SourceFixed | 0x00000800, 920 REV_w = REV, 921 REV32_x = REV | SixtyFourBits, 922 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, 923 CLZ = DataProcessing1SourceFixed | 0x00001000, 924 CLZ_w = CLZ, 925 CLZ_x = CLZ | SixtyFourBits, 926 CLS = DataProcessing1SourceFixed | 0x00001400, 927 CLS_w = CLS, 928 CLS_x = CLS | SixtyFourBits 929 }; 930 931 // Data processing 2 source. 932 enum DataProcessing2SourceOp { 933 DataProcessing2SourceFixed = 0x1AC00000, 934 DataProcessing2SourceFMask = 0x5FE00000, 935 DataProcessing2SourceMask = 0xFFE0FC00, 936 UDIV_w = DataProcessing2SourceFixed | 0x00000800, 937 UDIV_x = DataProcessing2SourceFixed | 0x80000800, 938 UDIV = UDIV_w, 939 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, 940 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, 941 SDIV = SDIV_w, 942 LSLV_w = DataProcessing2SourceFixed | 0x00002000, 943 LSLV_x = DataProcessing2SourceFixed | 0x80002000, 944 LSLV = LSLV_w, 945 LSRV_w = DataProcessing2SourceFixed | 0x00002400, 946 LSRV_x = DataProcessing2SourceFixed | 0x80002400, 947 LSRV = LSRV_w, 948 ASRV_w = DataProcessing2SourceFixed | 0x00002800, 949 ASRV_x = DataProcessing2SourceFixed | 0x80002800, 950 ASRV = ASRV_w, 951 RORV_w = DataProcessing2SourceFixed | 0x00002C00, 952 RORV_x = DataProcessing2SourceFixed | 0x80002C00, 953 RORV = RORV_w, 954 CRC32B = DataProcessing2SourceFixed | 0x00004000, 955 CRC32H = DataProcessing2SourceFixed | 0x00004400, 956 CRC32W = DataProcessing2SourceFixed | 0x00004800, 957 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, 958 CRC32CB = DataProcessing2SourceFixed | 0x00005000, 959 CRC32CH = DataProcessing2SourceFixed | 0x00005400, 960 CRC32CW = DataProcessing2SourceFixed | 0x00005800, 961 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 962 }; 963 964 // Data processing 3 source. 965 enum DataProcessing3SourceOp { 966 DataProcessing3SourceFixed = 0x1B000000, 967 DataProcessing3SourceFMask = 0x1F000000, 968 DataProcessing3SourceMask = 0xFFE08000, 969 MADD_w = DataProcessing3SourceFixed | 0x00000000, 970 MADD_x = DataProcessing3SourceFixed | 0x80000000, 971 MADD = MADD_w, 972 MSUB_w = DataProcessing3SourceFixed | 0x00008000, 973 MSUB_x = DataProcessing3SourceFixed | 0x80008000, 974 MSUB = MSUB_w, 975 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, 976 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, 977 SMULH_x = DataProcessing3SourceFixed | 0x80400000, 978 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, 979 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, 980 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 981 }; 982 983 // Floating point compare. 984 enum FPCompareOp { 985 FPCompareFixed = 0x1E202000, 986 FPCompareFMask = 0x5F203C00, 987 FPCompareMask = 0xFFE0FC1F, 988 FCMP_s = FPCompareFixed | 0x00000000, 989 FCMP_d = FPCompareFixed | FP64 | 0x00000000, 990 FCMP = FCMP_s, 991 FCMP_s_zero = FPCompareFixed | 0x00000008, 992 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, 993 FCMP_zero = FCMP_s_zero, 994 FCMPE_s = FPCompareFixed | 0x00000010, 995 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, 996 FCMPE_s_zero = FPCompareFixed | 0x00000018, 997 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018 998 }; 999 1000 // Floating point conditional compare. 1001 enum FPConditionalCompareOp { 1002 FPConditionalCompareFixed = 0x1E200400, 1003 FPConditionalCompareFMask = 0x5F200C00, 1004 FPConditionalCompareMask = 0xFFE00C10, 1005 FCCMP_s = FPConditionalCompareFixed | 0x00000000, 1006 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, 1007 FCCMP = FCCMP_s, 1008 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, 1009 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, 1010 FCCMPE = FCCMPE_s 1011 }; 1012 1013 // Floating point conditional select. 1014 enum FPConditionalSelectOp { 1015 FPConditionalSelectFixed = 0x1E200C00, 1016 FPConditionalSelectFMask = 0x5F200C00, 1017 FPConditionalSelectMask = 0xFFE00C00, 1018 FCSEL_s = FPConditionalSelectFixed | 0x00000000, 1019 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, 1020 FCSEL = FCSEL_s 1021 }; 1022 1023 // Floating point immediate. 1024 enum FPImmediateOp { 1025 FPImmediateFixed = 0x1E201000, 1026 FPImmediateFMask = 0x5F201C00, 1027 FPImmediateMask = 0xFFE01C00, 1028 FMOV_s_imm = FPImmediateFixed | 0x00000000, 1029 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 1030 }; 1031 1032 // Floating point data processing 1 source. 1033 enum FPDataProcessing1SourceOp { 1034 FPDataProcessing1SourceFixed = 0x1E204000, 1035 FPDataProcessing1SourceFMask = 0x5F207C00, 1036 FPDataProcessing1SourceMask = 0xFFFFFC00, 1037 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 1038 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 1039 FMOV = FMOV_s, 1040 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 1041 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 1042 FABS = FABS_s, 1043 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 1044 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 1045 FNEG = FNEG_s, 1046 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 1047 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 1048 FSQRT = FSQRT_s, 1049 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 1050 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 1051 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 1052 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 1053 FRINTN = FRINTN_s, 1054 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 1055 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 1056 FRINTP = FRINTP_s, 1057 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 1058 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 1059 FRINTM = FRINTM_s, 1060 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 1061 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 1062 FRINTZ = FRINTZ_s, 1063 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 1064 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 1065 FRINTA = FRINTA_s, 1066 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 1067 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 1068 FRINTX = FRINTX_s, 1069 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 1070 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 1071 FRINTI = FRINTI_s 1072 }; 1073 1074 // Floating point data processing 2 source. 1075 enum FPDataProcessing2SourceOp { 1076 FPDataProcessing2SourceFixed = 0x1E200800, 1077 FPDataProcessing2SourceFMask = 0x5F200C00, 1078 FPDataProcessing2SourceMask = 0xFFE0FC00, 1079 FMUL = FPDataProcessing2SourceFixed | 0x00000000, 1080 FMUL_s = FMUL, 1081 FMUL_d = FMUL | FP64, 1082 FDIV = FPDataProcessing2SourceFixed | 0x00001000, 1083 FDIV_s = FDIV, 1084 FDIV_d = FDIV | FP64, 1085 FADD = FPDataProcessing2SourceFixed | 0x00002000, 1086 FADD_s = FADD, 1087 FADD_d = FADD | FP64, 1088 FSUB = FPDataProcessing2SourceFixed | 0x00003000, 1089 FSUB_s = FSUB, 1090 FSUB_d = FSUB | FP64, 1091 FMAX = FPDataProcessing2SourceFixed | 0x00004000, 1092 FMAX_s = FMAX, 1093 FMAX_d = FMAX | FP64, 1094 FMIN = FPDataProcessing2SourceFixed | 0x00005000, 1095 FMIN_s = FMIN, 1096 FMIN_d = FMIN | FP64, 1097 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, 1098 FMAXNM_s = FMAXNM, 1099 FMAXNM_d = FMAXNM | FP64, 1100 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, 1101 FMINNM_s = FMINNM, 1102 FMINNM_d = FMINNM | FP64, 1103 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, 1104 FNMUL_s = FNMUL, 1105 FNMUL_d = FNMUL | FP64 1106 }; 1107 1108 // Floating point data processing 3 source. 1109 enum FPDataProcessing3SourceOp { 1110 FPDataProcessing3SourceFixed = 0x1F000000, 1111 FPDataProcessing3SourceFMask = 0x5F000000, 1112 FPDataProcessing3SourceMask = 0xFFE08000, 1113 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, 1114 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, 1115 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, 1116 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, 1117 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1118 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1119 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1120 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1121 }; 1122 1123 // Conversion between floating point and integer. 1124 enum FPIntegerConvertOp { 1125 FPIntegerConvertFixed = 0x1E200000, 1126 FPIntegerConvertFMask = 0x5F20FC00, 1127 FPIntegerConvertMask = 0xFFFFFC00, 1128 FCVTNS = FPIntegerConvertFixed | 0x00000000, 1129 FCVTNS_ws = FCVTNS, 1130 FCVTNS_xs = FCVTNS | SixtyFourBits, 1131 FCVTNS_wd = FCVTNS | FP64, 1132 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1133 FCVTNU = FPIntegerConvertFixed | 0x00010000, 1134 FCVTNU_ws = FCVTNU, 1135 FCVTNU_xs = FCVTNU | SixtyFourBits, 1136 FCVTNU_wd = FCVTNU | FP64, 1137 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1138 FCVTPS = FPIntegerConvertFixed | 0x00080000, 1139 FCVTPS_ws = FCVTPS, 1140 FCVTPS_xs = FCVTPS | SixtyFourBits, 1141 FCVTPS_wd = FCVTPS | FP64, 1142 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1143 FCVTPU = FPIntegerConvertFixed | 0x00090000, 1144 FCVTPU_ws = FCVTPU, 1145 FCVTPU_xs = FCVTPU | SixtyFourBits, 1146 FCVTPU_wd = FCVTPU | FP64, 1147 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1148 FCVTMS = FPIntegerConvertFixed | 0x00100000, 1149 FCVTMS_ws = FCVTMS, 1150 FCVTMS_xs = FCVTMS | SixtyFourBits, 1151 FCVTMS_wd = FCVTMS | FP64, 1152 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1153 FCVTMU = FPIntegerConvertFixed | 0x00110000, 1154 FCVTMU_ws = FCVTMU, 1155 FCVTMU_xs = FCVTMU | SixtyFourBits, 1156 FCVTMU_wd = FCVTMU | FP64, 1157 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1158 FCVTZS = FPIntegerConvertFixed | 0x00180000, 1159 FCVTZS_ws = FCVTZS, 1160 FCVTZS_xs = FCVTZS | SixtyFourBits, 1161 FCVTZS_wd = FCVTZS | FP64, 1162 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1163 FCVTZU = FPIntegerConvertFixed | 0x00190000, 1164 FCVTZU_ws = FCVTZU, 1165 FCVTZU_xs = FCVTZU | SixtyFourBits, 1166 FCVTZU_wd = FCVTZU | FP64, 1167 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1168 SCVTF = FPIntegerConvertFixed | 0x00020000, 1169 SCVTF_sw = SCVTF, 1170 SCVTF_sx = SCVTF | SixtyFourBits, 1171 SCVTF_dw = SCVTF | FP64, 1172 SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1173 UCVTF = FPIntegerConvertFixed | 0x00030000, 1174 UCVTF_sw = UCVTF, 1175 UCVTF_sx = UCVTF | SixtyFourBits, 1176 UCVTF_dw = UCVTF | FP64, 1177 UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1178 FCVTAS = FPIntegerConvertFixed | 0x00040000, 1179 FCVTAS_ws = FCVTAS, 1180 FCVTAS_xs = FCVTAS | SixtyFourBits, 1181 FCVTAS_wd = FCVTAS | FP64, 1182 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1183 FCVTAU = FPIntegerConvertFixed | 0x00050000, 1184 FCVTAU_ws = FCVTAU, 1185 FCVTAU_xs = FCVTAU | SixtyFourBits, 1186 FCVTAU_wd = FCVTAU | FP64, 1187 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1188 FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1189 FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1190 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1191 FMOV_dx = FMOV_sw | SixtyFourBits | FP64 1192 }; 1193 1194 // Conversion between fixed point and floating point. 1195 enum FPFixedPointConvertOp { 1196 FPFixedPointConvertFixed = 0x1E000000, 1197 FPFixedPointConvertFMask = 0x5F200000, 1198 FPFixedPointConvertMask = 0xFFFF0000, 1199 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1200 FCVTZS_ws_fixed = FCVTZS_fixed, 1201 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1202 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1203 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1204 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1205 FCVTZU_ws_fixed = FCVTZU_fixed, 1206 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1207 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1208 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1209 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1210 SCVTF_sw_fixed = SCVTF_fixed, 1211 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1212 SCVTF_dw_fixed = SCVTF_fixed | FP64, 1213 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1214 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1215 UCVTF_sw_fixed = UCVTF_fixed, 1216 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1217 UCVTF_dw_fixed = UCVTF_fixed | FP64, 1218 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1219 }; 1220 1221 // Unimplemented and unallocated instructions. These are defined to make fixed 1222 // bit assertion easier. 1223 enum UnimplementedOp { 1224 UnimplementedFixed = 0x00000000, 1225 UnimplementedFMask = 0x00000000 1226 }; 1227 1228 enum UnallocatedOp { 1229 UnallocatedFixed = 0x00000000, 1230 UnallocatedFMask = 0x00000000 1231 }; 1232 1233 } // namespace internal 1234 } // namespace v8 1235 1236 #endif // V8_ARM64_CONSTANTS_ARM64_H_ 1237
