1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 */ 31 32 33 #ifndef BRW_STRUCTS_H 34 #define BRW_STRUCTS_H 35 36 37 /** Number of general purpose registers (VS, WM, etc) */ 38 #define BRW_MAX_GRF 128 39 40 /** 41 * First GRF used for the MRF hack. 42 * 43 * On gen7, MRFs are no longer used, and contiguous GRFs are used instead. We 44 * haven't converted our compiler to be aware of this, so it asks for MRFs and 45 * brw_eu_emit.c quietly converts them to be accesses of the top GRFs. The 46 * register allocators have to be careful of this to avoid corrupting the "MRF"s 47 * with actual GRF allocations. 48 */ 49 #define GEN7_MRF_HACK_START 112. 50 51 /** Number of message register file registers */ 52 #define BRW_MAX_MRF 16 53 54 /* These seem to be passed around as function args, so it works out 55 * better to keep them as #defines: 56 */ 57 #define BRW_FLUSH_READ_CACHE 0x1 58 #define BRW_FLUSH_STATE_CACHE 0x2 59 #define BRW_INHIBIT_FLUSH_RENDER_CACHE 0x4 60 #define BRW_FLUSH_SNAPSHOT_COUNTERS 0x8 61 62 struct brw_urb_fence 63 { 64 struct 65 { 66 GLuint length:8; 67 GLuint vs_realloc:1; 68 GLuint gs_realloc:1; 69 GLuint clp_realloc:1; 70 GLuint sf_realloc:1; 71 GLuint vfe_realloc:1; 72 GLuint cs_realloc:1; 73 GLuint pad:2; 74 GLuint opcode:16; 75 } header; 76 77 struct 78 { 79 GLuint vs_fence:10; 80 GLuint gs_fence:10; 81 GLuint clp_fence:10; 82 GLuint pad:2; 83 } bits0; 84 85 struct 86 { 87 GLuint sf_fence:10; 88 GLuint vf_fence:10; 89 GLuint cs_fence:11; 90 GLuint pad:1; 91 } bits1; 92 }; 93 94 /* State structs for the various fixed function units: 95 */ 96 97 98 struct thread0 99 { 100 GLuint pad0:1; 101 GLuint grf_reg_count:3; 102 GLuint pad1:2; 103 GLuint kernel_start_pointer:26; /* Offset from GENERAL_STATE_BASE */ 104 }; 105 106 struct thread1 107 { 108 GLuint ext_halt_exception_enable:1; 109 GLuint sw_exception_enable:1; 110 GLuint mask_stack_exception_enable:1; 111 GLuint timeout_exception_enable:1; 112 GLuint illegal_op_exception_enable:1; 113 GLuint pad0:3; 114 GLuint depth_coef_urb_read_offset:6; /* WM only */ 115 GLuint pad1:2; 116 GLuint floating_point_mode:1; 117 GLuint thread_priority:1; 118 GLuint binding_table_entry_count:8; 119 GLuint pad3:5; 120 GLuint single_program_flow:1; 121 }; 122 123 struct thread2 124 { 125 GLuint per_thread_scratch_space:4; 126 GLuint pad0:6; 127 GLuint scratch_space_base_pointer:22; 128 }; 129 130 131 struct thread3 132 { 133 GLuint dispatch_grf_start_reg:4; 134 GLuint urb_entry_read_offset:6; 135 GLuint pad0:1; 136 GLuint urb_entry_read_length:6; 137 GLuint pad1:1; 138 GLuint const_urb_entry_read_offset:6; 139 GLuint pad2:1; 140 GLuint const_urb_entry_read_length:6; 141 GLuint pad3:1; 142 }; 143 144 145 146 struct brw_clip_unit_state 147 { 148 struct thread0 thread0; 149 struct 150 { 151 GLuint pad0:7; 152 GLuint sw_exception_enable:1; 153 GLuint pad1:3; 154 GLuint mask_stack_exception_enable:1; 155 GLuint pad2:1; 156 GLuint illegal_op_exception_enable:1; 157 GLuint pad3:2; 158 GLuint floating_point_mode:1; 159 GLuint thread_priority:1; 160 GLuint binding_table_entry_count:8; 161 GLuint pad4:5; 162 GLuint single_program_flow:1; 163 } thread1; 164 165 struct thread2 thread2; 166 struct thread3 thread3; 167 168 struct 169 { 170 GLuint pad0:9; 171 GLuint gs_output_stats:1; /* not always */ 172 GLuint stats_enable:1; 173 GLuint nr_urb_entries:7; 174 GLuint pad1:1; 175 GLuint urb_entry_allocation_size:5; 176 GLuint pad2:1; 177 GLuint max_threads:5; /* may be less */ 178 GLuint pad3:2; 179 } thread4; 180 181 struct 182 { 183 GLuint pad0:13; 184 GLuint clip_mode:3; 185 GLuint userclip_enable_flags:8; 186 GLuint userclip_must_clip:1; 187 GLuint negative_w_clip_test:1; 188 GLuint guard_band_enable:1; 189 GLuint viewport_z_clip_enable:1; 190 GLuint viewport_xy_clip_enable:1; 191 GLuint vertex_position_space:1; 192 GLuint api_mode:1; 193 GLuint pad2:1; 194 } clip5; 195 196 struct 197 { 198 GLuint pad0:5; 199 GLuint clipper_viewport_state_ptr:27; 200 } clip6; 201 202 203 GLfloat viewport_xmin; 204 GLfloat viewport_xmax; 205 GLfloat viewport_ymin; 206 GLfloat viewport_ymax; 207 }; 208 209 struct gen6_blend_state 210 { 211 struct { 212 GLuint dest_blend_factor:5; 213 GLuint source_blend_factor:5; 214 GLuint pad3:1; 215 GLuint blend_func:3; 216 GLuint pad2:1; 217 GLuint ia_dest_blend_factor:5; 218 GLuint ia_source_blend_factor:5; 219 GLuint pad1:1; 220 GLuint ia_blend_func:3; 221 GLuint pad0:1; 222 GLuint ia_blend_enable:1; 223 GLuint blend_enable:1; 224 } blend0; 225 226 struct { 227 GLuint post_blend_clamp_enable:1; 228 GLuint pre_blend_clamp_enable:1; 229 GLuint clamp_range:2; 230 GLuint pad0:4; 231 GLuint x_dither_offset:2; 232 GLuint y_dither_offset:2; 233 GLuint dither_enable:1; 234 GLuint alpha_test_func:3; 235 GLuint alpha_test_enable:1; 236 GLuint pad1:1; 237 GLuint logic_op_func:4; 238 GLuint logic_op_enable:1; 239 GLuint pad2:1; 240 GLuint write_disable_b:1; 241 GLuint write_disable_g:1; 242 GLuint write_disable_r:1; 243 GLuint write_disable_a:1; 244 GLuint pad3:1; 245 GLuint alpha_to_coverage_dither:1; 246 GLuint alpha_to_one:1; 247 GLuint alpha_to_coverage:1; 248 } blend1; 249 }; 250 251 struct gen6_color_calc_state 252 { 253 struct { 254 GLuint alpha_test_format:1; 255 GLuint pad0:14; 256 GLuint round_disable:1; 257 GLuint bf_stencil_ref:8; 258 GLuint stencil_ref:8; 259 } cc0; 260 261 union { 262 GLfloat alpha_ref_f; 263 struct { 264 GLuint ui:8; 265 GLuint pad0:24; 266 } alpha_ref_fi; 267 } cc1; 268 269 GLfloat constant_r; 270 GLfloat constant_g; 271 GLfloat constant_b; 272 GLfloat constant_a; 273 }; 274 275 struct gen6_depth_stencil_state 276 { 277 struct { 278 GLuint pad0:3; 279 GLuint bf_stencil_pass_depth_pass_op:3; 280 GLuint bf_stencil_pass_depth_fail_op:3; 281 GLuint bf_stencil_fail_op:3; 282 GLuint bf_stencil_func:3; 283 GLuint bf_stencil_enable:1; 284 GLuint pad1:2; 285 GLuint stencil_write_enable:1; 286 GLuint stencil_pass_depth_pass_op:3; 287 GLuint stencil_pass_depth_fail_op:3; 288 GLuint stencil_fail_op:3; 289 GLuint stencil_func:3; 290 GLuint stencil_enable:1; 291 } ds0; 292 293 struct { 294 GLuint bf_stencil_write_mask:8; 295 GLuint bf_stencil_test_mask:8; 296 GLuint stencil_write_mask:8; 297 GLuint stencil_test_mask:8; 298 } ds1; 299 300 struct { 301 GLuint pad0:26; 302 GLuint depth_write_enable:1; 303 GLuint depth_test_func:3; 304 GLuint pad1:1; 305 GLuint depth_test_enable:1; 306 } ds2; 307 }; 308 309 struct brw_cc_unit_state 310 { 311 struct 312 { 313 GLuint pad0:3; 314 GLuint bf_stencil_pass_depth_pass_op:3; 315 GLuint bf_stencil_pass_depth_fail_op:3; 316 GLuint bf_stencil_fail_op:3; 317 GLuint bf_stencil_func:3; 318 GLuint bf_stencil_enable:1; 319 GLuint pad1:2; 320 GLuint stencil_write_enable:1; 321 GLuint stencil_pass_depth_pass_op:3; 322 GLuint stencil_pass_depth_fail_op:3; 323 GLuint stencil_fail_op:3; 324 GLuint stencil_func:3; 325 GLuint stencil_enable:1; 326 } cc0; 327 328 329 struct 330 { 331 GLuint bf_stencil_ref:8; 332 GLuint stencil_write_mask:8; 333 GLuint stencil_test_mask:8; 334 GLuint stencil_ref:8; 335 } cc1; 336 337 338 struct 339 { 340 GLuint logicop_enable:1; 341 GLuint pad0:10; 342 GLuint depth_write_enable:1; 343 GLuint depth_test_function:3; 344 GLuint depth_test:1; 345 GLuint bf_stencil_write_mask:8; 346 GLuint bf_stencil_test_mask:8; 347 } cc2; 348 349 350 struct 351 { 352 GLuint pad0:8; 353 GLuint alpha_test_func:3; 354 GLuint alpha_test:1; 355 GLuint blend_enable:1; 356 GLuint ia_blend_enable:1; 357 GLuint pad1:1; 358 GLuint alpha_test_format:1; 359 GLuint pad2:16; 360 } cc3; 361 362 struct 363 { 364 GLuint pad0:5; 365 GLuint cc_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ 366 } cc4; 367 368 struct 369 { 370 GLuint pad0:2; 371 GLuint ia_dest_blend_factor:5; 372 GLuint ia_src_blend_factor:5; 373 GLuint ia_blend_function:3; 374 GLuint statistics_enable:1; 375 GLuint logicop_func:4; 376 GLuint pad1:11; 377 GLuint dither_enable:1; 378 } cc5; 379 380 struct 381 { 382 GLuint clamp_post_alpha_blend:1; 383 GLuint clamp_pre_alpha_blend:1; 384 GLuint clamp_range:2; 385 GLuint pad0:11; 386 GLuint y_dither_offset:2; 387 GLuint x_dither_offset:2; 388 GLuint dest_blend_factor:5; 389 GLuint src_blend_factor:5; 390 GLuint blend_function:3; 391 } cc6; 392 393 struct { 394 union { 395 GLfloat f; 396 GLubyte ub[4]; 397 } alpha_ref; 398 } cc7; 399 }; 400 401 struct brw_sf_unit_state 402 { 403 struct thread0 thread0; 404 struct thread1 thread1; 405 struct thread2 thread2; 406 struct thread3 thread3; 407 408 struct 409 { 410 GLuint pad0:10; 411 GLuint stats_enable:1; 412 GLuint nr_urb_entries:7; 413 GLuint pad1:1; 414 GLuint urb_entry_allocation_size:5; 415 GLuint pad2:1; 416 GLuint max_threads:6; 417 GLuint pad3:1; 418 } thread4; 419 420 struct 421 { 422 GLuint front_winding:1; 423 GLuint viewport_transform:1; 424 GLuint pad0:3; 425 GLuint sf_viewport_state_offset:27; /* Offset from GENERAL_STATE_BASE */ 426 } sf5; 427 428 struct 429 { 430 GLuint pad0:9; 431 GLuint dest_org_vbias:4; 432 GLuint dest_org_hbias:4; 433 GLuint scissor:1; 434 GLuint disable_2x2_trifilter:1; 435 GLuint disable_zero_pix_trifilter:1; 436 GLuint point_rast_rule:2; 437 GLuint line_endcap_aa_region_width:2; 438 GLuint line_width:4; 439 GLuint fast_scissor_disable:1; 440 GLuint cull_mode:2; 441 GLuint aa_enable:1; 442 } sf6; 443 444 struct 445 { 446 GLuint point_size:11; 447 GLuint use_point_size_state:1; 448 GLuint subpixel_precision:1; 449 GLuint sprite_point:1; 450 GLuint pad0:10; 451 GLuint aa_line_distance_mode:1; 452 GLuint trifan_pv:2; 453 GLuint linestrip_pv:2; 454 GLuint tristrip_pv:2; 455 GLuint line_last_pixel_enable:1; 456 } sf7; 457 458 }; 459 460 struct gen6_scissor_rect 461 { 462 GLuint xmin:16; 463 GLuint ymin:16; 464 GLuint xmax:16; 465 GLuint ymax:16; 466 }; 467 468 struct brw_gs_unit_state 469 { 470 struct thread0 thread0; 471 struct thread1 thread1; 472 struct thread2 thread2; 473 struct thread3 thread3; 474 475 struct 476 { 477 GLuint pad0:8; 478 GLuint rendering_enable:1; /* for Ironlake */ 479 GLuint pad4:1; 480 GLuint stats_enable:1; 481 GLuint nr_urb_entries:7; 482 GLuint pad1:1; 483 GLuint urb_entry_allocation_size:5; 484 GLuint pad2:1; 485 GLuint max_threads:5; 486 GLuint pad3:2; 487 } thread4; 488 489 struct 490 { 491 GLuint sampler_count:3; 492 GLuint pad0:2; 493 GLuint sampler_state_pointer:27; 494 } gs5; 495 496 497 struct 498 { 499 GLuint max_vp_index:4; 500 GLuint pad0:12; 501 GLuint svbi_post_inc_value:10; 502 GLuint pad1:1; 503 GLuint svbi_post_inc_enable:1; 504 GLuint svbi_payload:1; 505 GLuint discard_adjaceny:1; 506 GLuint reorder_enable:1; 507 GLuint pad2:1; 508 } gs6; 509 }; 510 511 512 struct brw_vs_unit_state 513 { 514 struct thread0 thread0; 515 struct thread1 thread1; 516 struct thread2 thread2; 517 struct thread3 thread3; 518 519 struct 520 { 521 GLuint pad0:10; 522 GLuint stats_enable:1; 523 GLuint nr_urb_entries:7; 524 GLuint pad1:1; 525 GLuint urb_entry_allocation_size:5; 526 GLuint pad2:1; 527 GLuint max_threads:6; 528 GLuint pad3:1; 529 } thread4; 530 531 struct 532 { 533 GLuint sampler_count:3; 534 GLuint pad0:2; 535 GLuint sampler_state_pointer:27; 536 } vs5; 537 538 struct 539 { 540 GLuint vs_enable:1; 541 GLuint vert_cache_disable:1; 542 GLuint pad0:30; 543 } vs6; 544 }; 545 546 547 struct brw_wm_unit_state 548 { 549 struct thread0 thread0; 550 struct thread1 thread1; 551 struct thread2 thread2; 552 struct thread3 thread3; 553 554 struct { 555 GLuint stats_enable:1; 556 GLuint depth_buffer_clear:1; 557 GLuint sampler_count:3; 558 GLuint sampler_state_pointer:27; 559 } wm4; 560 561 struct 562 { 563 GLuint enable_8_pix:1; 564 GLuint enable_16_pix:1; 565 GLuint enable_32_pix:1; 566 GLuint enable_con_32_pix:1; 567 GLuint enable_con_64_pix:1; 568 GLuint pad0:1; 569 570 /* These next four bits are for Ironlake+ */ 571 GLuint fast_span_coverage_enable:1; 572 GLuint depth_buffer_clear:1; 573 GLuint depth_buffer_resolve_enable:1; 574 GLuint hierarchical_depth_buffer_resolve_enable:1; 575 576 GLuint legacy_global_depth_bias:1; 577 GLuint line_stipple:1; 578 GLuint depth_offset:1; 579 GLuint polygon_stipple:1; 580 GLuint line_aa_region_width:2; 581 GLuint line_endcap_aa_region_width:2; 582 GLuint early_depth_test:1; 583 GLuint thread_dispatch_enable:1; 584 GLuint program_uses_depth:1; 585 GLuint program_computes_depth:1; 586 GLuint program_uses_killpixel:1; 587 GLuint legacy_line_rast: 1; 588 GLuint transposed_urb_read_enable:1; 589 GLuint max_threads:7; 590 } wm5; 591 592 GLfloat global_depth_offset_constant; 593 GLfloat global_depth_offset_scale; 594 595 /* for Ironlake only */ 596 struct { 597 GLuint pad0:1; 598 GLuint grf_reg_count_1:3; 599 GLuint pad1:2; 600 GLuint kernel_start_pointer_1:26; 601 } wm8; 602 603 struct { 604 GLuint pad0:1; 605 GLuint grf_reg_count_2:3; 606 GLuint pad1:2; 607 GLuint kernel_start_pointer_2:26; 608 } wm9; 609 610 struct { 611 GLuint pad0:1; 612 GLuint grf_reg_count_3:3; 613 GLuint pad1:2; 614 GLuint kernel_start_pointer_3:26; 615 } wm10; 616 }; 617 618 struct brw_sampler_default_color { 619 GLfloat color[4]; 620 }; 621 622 struct gen5_sampler_default_color { 623 uint8_t ub[4]; 624 float f[4]; 625 uint16_t hf[4]; 626 uint16_t us[4]; 627 int16_t s[4]; 628 uint8_t b[4]; 629 }; 630 631 struct brw_sampler_state 632 { 633 634 struct 635 { 636 GLuint shadow_function:3; 637 GLuint lod_bias:11; 638 GLuint min_filter:3; 639 GLuint mag_filter:3; 640 GLuint mip_filter:2; 641 GLuint base_level:5; 642 GLuint min_mag_neq:1; 643 GLuint lod_preclamp:1; 644 GLuint default_color_mode:1; 645 GLuint pad0:1; 646 GLuint disable:1; 647 } ss0; 648 649 struct 650 { 651 GLuint r_wrap_mode:3; 652 GLuint t_wrap_mode:3; 653 GLuint s_wrap_mode:3; 654 GLuint cube_control_mode:1; 655 GLuint pad:2; 656 GLuint max_lod:10; 657 GLuint min_lod:10; 658 } ss1; 659 660 661 struct 662 { 663 GLuint pad:5; 664 GLuint default_color_pointer:27; 665 } ss2; 666 667 struct 668 { 669 GLuint non_normalized_coord:1; 670 GLuint pad:12; 671 GLuint address_round:6; 672 GLuint max_aniso:3; 673 GLuint chroma_key_mode:1; 674 GLuint chroma_key_index:2; 675 GLuint chroma_key_enable:1; 676 GLuint monochrome_filter_width:3; 677 GLuint monochrome_filter_height:3; 678 } ss3; 679 }; 680 681 struct gen7_sampler_state 682 { 683 struct 684 { 685 GLuint aniso_algorithm:1; 686 GLuint lod_bias:13; 687 GLuint min_filter:3; 688 GLuint mag_filter:3; 689 GLuint mip_filter:2; 690 GLuint base_level:5; 691 GLuint pad1:1; 692 GLuint lod_preclamp:1; 693 GLuint default_color_mode:1; 694 GLuint pad0:1; 695 GLuint disable:1; 696 } ss0; 697 698 struct 699 { 700 GLuint cube_control_mode:1; 701 GLuint shadow_function:3; 702 GLuint pad:4; 703 GLuint max_lod:12; 704 GLuint min_lod:12; 705 } ss1; 706 707 struct 708 { 709 GLuint pad:5; 710 GLuint default_color_pointer:27; 711 } ss2; 712 713 struct 714 { 715 GLuint r_wrap_mode:3; 716 GLuint t_wrap_mode:3; 717 GLuint s_wrap_mode:3; 718 GLuint pad:1; 719 GLuint non_normalized_coord:1; 720 GLuint trilinear_quality:2; 721 GLuint address_round:6; 722 GLuint max_aniso:3; 723 GLuint chroma_key_mode:1; 724 GLuint chroma_key_index:2; 725 GLuint chroma_key_enable:1; 726 GLuint pad0:6; 727 } ss3; 728 }; 729 730 struct brw_clipper_viewport 731 { 732 GLfloat xmin; 733 GLfloat xmax; 734 GLfloat ymin; 735 GLfloat ymax; 736 }; 737 738 struct brw_cc_viewport 739 { 740 GLfloat min_depth; 741 GLfloat max_depth; 742 }; 743 744 struct brw_sf_viewport 745 { 746 struct { 747 GLfloat m00; 748 GLfloat m11; 749 GLfloat m22; 750 GLfloat m30; 751 GLfloat m31; 752 GLfloat m32; 753 } viewport; 754 755 /* scissor coordinates are inclusive */ 756 struct { 757 GLshort xmin; 758 GLshort ymin; 759 GLshort xmax; 760 GLshort ymax; 761 } scissor; 762 }; 763 764 struct gen6_sf_viewport { 765 GLfloat m00; 766 GLfloat m11; 767 GLfloat m22; 768 GLfloat m30; 769 GLfloat m31; 770 GLfloat m32; 771 }; 772 773 struct gen7_sf_clip_viewport { 774 struct { 775 GLfloat m00; 776 GLfloat m11; 777 GLfloat m22; 778 GLfloat m30; 779 GLfloat m31; 780 GLfloat m32; 781 } viewport; 782 783 GLuint pad0[2]; 784 785 struct { 786 GLfloat xmin; 787 GLfloat xmax; 788 GLfloat ymin; 789 GLfloat ymax; 790 } guardband; 791 792 GLfloat pad1[4]; 793 }; 794 795 /* volume 5c Shared Functions - 1.13.4.1.2 */ 796 struct gen7_surface_state 797 { 798 struct { 799 GLuint cube_pos_z:1; 800 GLuint cube_neg_z:1; 801 GLuint cube_pos_y:1; 802 GLuint cube_neg_y:1; 803 GLuint cube_pos_x:1; 804 GLuint cube_neg_x:1; 805 GLuint pad2:2; 806 GLuint render_cache_read_write:1; 807 GLuint pad1:1; 808 GLuint surface_array_spacing:1; 809 GLuint vert_line_stride_ofs:1; 810 GLuint vert_line_stride:1; 811 GLuint tile_walk:1; 812 GLuint tiled_surface:1; 813 GLuint horizontal_alignment:1; 814 GLuint vertical_alignment:2; 815 GLuint surface_format:9; /**< BRW_SURFACEFORMAT_x */ 816 GLuint pad0:1; 817 GLuint is_array:1; 818 GLuint surface_type:3; /**< BRW_SURFACE_1D/2D/3D/CUBE */ 819 } ss0; 820 821 struct { 822 GLuint base_addr; 823 } ss1; 824 825 struct { 826 GLuint width:14; 827 GLuint pad1:2; 828 GLuint height:14; 829 GLuint pad0:2; 830 } ss2; 831 832 struct { 833 GLuint pitch:18; 834 GLuint pad:3; 835 GLuint depth:11; 836 } ss3; 837 838 struct { 839 GLuint multisample_position_palette_index:3; 840 GLuint num_multisamples:3; 841 GLuint multisampled_surface_storage_format:1; 842 GLuint render_target_view_extent:11; 843 GLuint min_array_elt:11; 844 GLuint rotation:2; 845 GLuint pad0:1; 846 } ss4; 847 848 struct { 849 GLuint mip_count:4; 850 GLuint min_lod:4; 851 GLuint pad1:12; 852 GLuint y_offset:4; 853 GLuint pad0:1; 854 GLuint x_offset:7; 855 } ss5; 856 857 union { 858 GLuint raw_data; 859 struct { 860 GLuint y_offset_for_uv_plane:14; 861 GLuint pad1:2; 862 GLuint x_offset_for_uv_plane:14; 863 GLuint pad0:2; 864 } planar; /** Interpretation when Surface Format == PLANAR */ 865 struct { 866 GLuint mcs_enable:1; 867 GLuint append_counter_enable:1; 868 GLuint pad:4; 869 GLuint append_counter_address:26; 870 } mcs_disabled; /** Interpretation when mcs_enable == 0 */ 871 struct { 872 GLuint mcs_enable:1; 873 GLuint pad:2; 874 GLuint mcs_surface_pitch:9; 875 GLuint mcs_base_address:20; 876 } mcs_enabled; /** Interpretation when mcs_enable == 1 */ 877 } ss6; 878 879 struct { 880 GLuint resource_min_lod:12; 881 882 /* Only on Haswell */ 883 GLuint pad0:4; 884 GLuint shader_channel_select_a:3; 885 GLuint shader_channel_select_b:3; 886 GLuint shader_channel_select_g:3; 887 GLuint shader_channel_select_r:3; 888 889 GLuint alpha_clear_color:1; 890 GLuint blue_clear_color:1; 891 GLuint green_clear_color:1; 892 GLuint red_clear_color:1; 893 } ss7; 894 }; 895 896 897 struct brw_vertex_element_state 898 { 899 struct 900 { 901 GLuint src_offset:11; 902 GLuint pad:5; 903 GLuint src_format:9; 904 GLuint pad0:1; 905 GLuint valid:1; 906 GLuint vertex_buffer_index:5; 907 } ve0; 908 909 struct 910 { 911 GLuint dst_offset:8; 912 GLuint pad:8; 913 GLuint vfcomponent3:4; 914 GLuint vfcomponent2:4; 915 GLuint vfcomponent1:4; 916 GLuint vfcomponent0:4; 917 } ve1; 918 }; 919 920 struct brw_urb_immediate { 921 GLuint opcode:4; 922 GLuint offset:6; 923 GLuint swizzle_control:2; 924 GLuint pad:1; 925 GLuint allocate:1; 926 GLuint used:1; 927 GLuint complete:1; 928 GLuint response_length:4; 929 GLuint msg_length:4; 930 GLuint msg_target:4; 931 GLuint pad1:3; 932 GLuint end_of_thread:1; 933 }; 934 935 /* Instruction format for the execution units: 936 */ 937 938 struct brw_instruction 939 { 940 struct 941 { 942 GLuint opcode:7; 943 GLuint pad:1; 944 GLuint access_mode:1; 945 GLuint mask_control:1; 946 GLuint dependency_control:2; 947 GLuint compression_control:2; /* gen6: quater control */ 948 GLuint thread_control:2; 949 GLuint predicate_control:4; 950 GLuint predicate_inverse:1; 951 GLuint execution_size:3; 952 /** 953 * Conditional Modifier for most instructions. On Gen6+, this is also 954 * used for the SEND instruction's Message Target/SFID. 955 */ 956 GLuint destreg__conditionalmod:4; 957 GLuint acc_wr_control:1; 958 GLuint cmpt_control:1; 959 GLuint debug_control:1; 960 GLuint saturate:1; 961 } header; 962 963 union { 964 struct 965 { 966 GLuint dest_reg_file:2; 967 GLuint dest_reg_type:3; 968 GLuint src0_reg_file:2; 969 GLuint src0_reg_type:3; 970 GLuint src1_reg_file:2; 971 GLuint src1_reg_type:3; 972 GLuint pad:1; 973 GLuint dest_subreg_nr:5; 974 GLuint dest_reg_nr:8; 975 GLuint dest_horiz_stride:2; 976 GLuint dest_address_mode:1; 977 } da1; 978 979 struct 980 { 981 GLuint dest_reg_file:2; 982 GLuint dest_reg_type:3; 983 GLuint src0_reg_file:2; 984 GLuint src0_reg_type:3; 985 GLuint src1_reg_file:2; /* 0x00000c00 */ 986 GLuint src1_reg_type:3; /* 0x00007000 */ 987 GLuint pad:1; 988 GLint dest_indirect_offset:10; /* offset against the deref'd address reg */ 989 GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */ 990 GLuint dest_horiz_stride:2; 991 GLuint dest_address_mode:1; 992 } ia1; 993 994 struct 995 { 996 GLuint dest_reg_file:2; 997 GLuint dest_reg_type:3; 998 GLuint src0_reg_file:2; 999 GLuint src0_reg_type:3; 1000 GLuint src1_reg_file:2; 1001 GLuint src1_reg_type:3; 1002 GLuint pad:1; 1003 GLuint dest_writemask:4; 1004 GLuint dest_subreg_nr:1; 1005 GLuint dest_reg_nr:8; 1006 GLuint dest_horiz_stride:2; 1007 GLuint dest_address_mode:1; 1008 } da16; 1009 1010 struct 1011 { 1012 GLuint dest_reg_file:2; 1013 GLuint dest_reg_type:3; 1014 GLuint src0_reg_file:2; 1015 GLuint src0_reg_type:3; 1016 GLuint pad0:6; 1017 GLuint dest_writemask:4; 1018 GLint dest_indirect_offset:6; 1019 GLuint dest_subreg_nr:3; 1020 GLuint dest_horiz_stride:2; 1021 GLuint dest_address_mode:1; 1022 } ia16; 1023 1024 struct { 1025 GLuint dest_reg_file:2; 1026 GLuint dest_reg_type:3; 1027 GLuint src0_reg_file:2; 1028 GLuint src0_reg_type:3; 1029 GLuint src1_reg_file:2; 1030 GLuint src1_reg_type:3; 1031 GLuint pad:1; 1032 1033 GLint jump_count:16; 1034 } branch_gen6; 1035 1036 struct { 1037 GLuint dest_reg_file:1; 1038 GLuint flag_subreg_num:1; 1039 GLuint pad0:2; 1040 GLuint src0_abs:1; 1041 GLuint src0_negate:1; 1042 GLuint src1_abs:1; 1043 GLuint src1_negate:1; 1044 GLuint src2_abs:1; 1045 GLuint src2_negate:1; 1046 GLuint pad1:7; 1047 GLuint dest_writemask:4; 1048 GLuint dest_subreg_nr:3; 1049 GLuint dest_reg_nr:8; 1050 } da3src; 1051 } bits1; 1052 1053 1054 union { 1055 struct 1056 { 1057 GLuint src0_subreg_nr:5; 1058 GLuint src0_reg_nr:8; 1059 GLuint src0_abs:1; 1060 GLuint src0_negate:1; 1061 GLuint src0_address_mode:1; 1062 GLuint src0_horiz_stride:2; 1063 GLuint src0_width:3; 1064 GLuint src0_vert_stride:4; 1065 GLuint flag_reg_nr:1; 1066 GLuint pad:6; 1067 } da1; 1068 1069 struct 1070 { 1071 GLint src0_indirect_offset:10; 1072 GLuint src0_subreg_nr:3; 1073 GLuint src0_abs:1; 1074 GLuint src0_negate:1; 1075 GLuint src0_address_mode:1; 1076 GLuint src0_horiz_stride:2; 1077 GLuint src0_width:3; 1078 GLuint src0_vert_stride:4; 1079 GLuint flag_reg_nr:1; 1080 GLuint pad:6; 1081 } ia1; 1082 1083 struct 1084 { 1085 GLuint src0_swz_x:2; 1086 GLuint src0_swz_y:2; 1087 GLuint src0_subreg_nr:1; 1088 GLuint src0_reg_nr:8; 1089 GLuint src0_abs:1; 1090 GLuint src0_negate:1; 1091 GLuint src0_address_mode:1; 1092 GLuint src0_swz_z:2; 1093 GLuint src0_swz_w:2; 1094 GLuint pad0:1; 1095 GLuint src0_vert_stride:4; 1096 GLuint flag_reg_nr:1; 1097 GLuint pad1:6; 1098 } da16; 1099 1100 struct 1101 { 1102 GLuint src0_swz_x:2; 1103 GLuint src0_swz_y:2; 1104 GLint src0_indirect_offset:6; 1105 GLuint src0_subreg_nr:3; 1106 GLuint src0_abs:1; 1107 GLuint src0_negate:1; 1108 GLuint src0_address_mode:1; 1109 GLuint src0_swz_z:2; 1110 GLuint src0_swz_w:2; 1111 GLuint pad0:1; 1112 GLuint src0_vert_stride:4; 1113 GLuint flag_reg_nr:1; 1114 GLuint pad1:6; 1115 } ia16; 1116 1117 /* Extended Message Descriptor for Ironlake (Gen5) SEND instruction. 1118 * 1119 * Does not apply to Gen6+. The SFID/message target moved to bits 1120 * 27:24 of the header (destreg__conditionalmod); EOT is in bits3. 1121 */ 1122 struct 1123 { 1124 GLuint pad:26; 1125 GLuint end_of_thread:1; 1126 GLuint pad1:1; 1127 GLuint sfid:4; 1128 } send_gen5; /* for Ironlake only */ 1129 1130 struct { 1131 GLuint src0_rep_ctrl:1; 1132 GLuint src0_swizzle:8; 1133 GLuint src0_subreg_nr:3; 1134 GLuint src0_reg_nr:8; 1135 GLuint pad0:1; 1136 GLuint src1_rep_ctrl:1; 1137 GLuint src1_swizzle:8; 1138 GLuint src1_subreg_nr_low:2; 1139 } da3src; 1140 } bits2; 1141 1142 union 1143 { 1144 struct 1145 { 1146 GLuint src1_subreg_nr:5; 1147 GLuint src1_reg_nr:8; 1148 GLuint src1_abs:1; 1149 GLuint src1_negate:1; 1150 GLuint src1_address_mode:1; 1151 GLuint src1_horiz_stride:2; 1152 GLuint src1_width:3; 1153 GLuint src1_vert_stride:4; 1154 GLuint pad0:7; 1155 } da1; 1156 1157 struct 1158 { 1159 GLuint src1_swz_x:2; 1160 GLuint src1_swz_y:2; 1161 GLuint src1_subreg_nr:1; 1162 GLuint src1_reg_nr:8; 1163 GLuint src1_abs:1; 1164 GLuint src1_negate:1; 1165 GLuint src1_address_mode:1; 1166 GLuint src1_swz_z:2; 1167 GLuint src1_swz_w:2; 1168 GLuint pad1:1; 1169 GLuint src1_vert_stride:4; 1170 GLuint pad2:7; 1171 } da16; 1172 1173 struct 1174 { 1175 GLint src1_indirect_offset:10; 1176 GLuint src1_subreg_nr:3; 1177 GLuint src1_abs:1; 1178 GLuint src1_negate:1; 1179 GLuint src1_address_mode:1; 1180 GLuint src1_horiz_stride:2; 1181 GLuint src1_width:3; 1182 GLuint src1_vert_stride:4; 1183 GLuint flag_reg_nr:1; 1184 GLuint pad1:6; 1185 } ia1; 1186 1187 struct 1188 { 1189 GLuint src1_swz_x:2; 1190 GLuint src1_swz_y:2; 1191 GLint src1_indirect_offset:6; 1192 GLuint src1_subreg_nr:3; 1193 GLuint src1_abs:1; 1194 GLuint src1_negate:1; 1195 GLuint pad0:1; 1196 GLuint src1_swz_z:2; 1197 GLuint src1_swz_w:2; 1198 GLuint pad1:1; 1199 GLuint src1_vert_stride:4; 1200 GLuint flag_reg_nr:1; 1201 GLuint pad2:6; 1202 } ia16; 1203 1204 1205 struct 1206 { 1207 GLint jump_count:16; /* note: signed */ 1208 GLuint pop_count:4; 1209 GLuint pad0:12; 1210 } if_else; 1211 1212 /* This is also used for gen7 IF/ELSE instructions */ 1213 struct 1214 { 1215 /* Signed jump distance to the ip to jump to if all channels 1216 * are disabled after the break or continue. It should point 1217 * to the end of the innermost control flow block, as that's 1218 * where some channel could get re-enabled. 1219 */ 1220 int jip:16; 1221 1222 /* Signed jump distance to the location to resume execution 1223 * of this channel if it's enabled for the break or continue. 1224 */ 1225 int uip:16; 1226 } break_cont; 1227 1228 /** 1229 * \defgroup SEND instructions / Message Descriptors 1230 * 1231 * @{ 1232 */ 1233 1234 /** 1235 * Generic Message Descriptor for Gen4 SEND instructions. The structs 1236 * below expand function_control to something specific for their 1237 * message. Due to struct packing issues, they duplicate these bits. 1238 * 1239 * See the G45 PRM, Volume 4, Table 14-15. 1240 */ 1241 struct { 1242 GLuint function_control:16; 1243 GLuint response_length:4; 1244 GLuint msg_length:4; 1245 GLuint msg_target:4; 1246 GLuint pad1:3; 1247 GLuint end_of_thread:1; 1248 } generic; 1249 1250 /** 1251 * Generic Message Descriptor for Gen5-7 SEND instructions. 1252 * 1253 * See the Sandybridge PRM, Volume 2 Part 2, Table 8-15. (Sadly, most 1254 * of the information on the SEND instruction is missing from the public 1255 * Ironlake PRM.) 1256 * 1257 * The table claims that bit 31 is reserved/MBZ on Gen6+, but it lies. 1258 * According to the SEND instruction description: 1259 * "The MSb of the message description, the EOT field, always comes from 1260 * bit 127 of the instruction word"...which is bit 31 of this field. 1261 */ 1262 struct { 1263 GLuint function_control:19; 1264 GLuint header_present:1; 1265 GLuint response_length:5; 1266 GLuint msg_length:4; 1267 GLuint pad1:2; 1268 GLuint end_of_thread:1; 1269 } generic_gen5; 1270 1271 /** G45 PRM, Volume 4, Section 6.1.1.1 */ 1272 struct { 1273 GLuint function:4; 1274 GLuint int_type:1; 1275 GLuint precision:1; 1276 GLuint saturate:1; 1277 GLuint data_type:1; 1278 GLuint pad0:8; 1279 GLuint response_length:4; 1280 GLuint msg_length:4; 1281 GLuint msg_target:4; 1282 GLuint pad1:3; 1283 GLuint end_of_thread:1; 1284 } math; 1285 1286 /** Ironlake PRM, Volume 4 Part 1, Section 6.1.1.1 */ 1287 struct { 1288 GLuint function:4; 1289 GLuint int_type:1; 1290 GLuint precision:1; 1291 GLuint saturate:1; 1292 GLuint data_type:1; 1293 GLuint snapshot:1; 1294 GLuint pad0:10; 1295 GLuint header_present:1; 1296 GLuint response_length:5; 1297 GLuint msg_length:4; 1298 GLuint pad1:2; 1299 GLuint end_of_thread:1; 1300 } math_gen5; 1301 1302 /** G45 PRM, Volume 4, Section 4.8.1.1.1 [DevBW] and [DevCL] */ 1303 struct { 1304 GLuint binding_table_index:8; 1305 GLuint sampler:4; 1306 GLuint return_format:2; 1307 GLuint msg_type:2; 1308 GLuint response_length:4; 1309 GLuint msg_length:4; 1310 GLuint msg_target:4; 1311 GLuint pad1:3; 1312 GLuint end_of_thread:1; 1313 } sampler; 1314 1315 /** G45 PRM, Volume 4, Section 4.8.1.1.2 [DevCTG] */ 1316 struct { 1317 GLuint binding_table_index:8; 1318 GLuint sampler:4; 1319 GLuint msg_type:4; 1320 GLuint response_length:4; 1321 GLuint msg_length:4; 1322 GLuint msg_target:4; 1323 GLuint pad1:3; 1324 GLuint end_of_thread:1; 1325 } sampler_g4x; 1326 1327 /** Ironlake PRM, Volume 4 Part 1, Section 4.11.1.1.3 */ 1328 struct { 1329 GLuint binding_table_index:8; 1330 GLuint sampler:4; 1331 GLuint msg_type:4; 1332 GLuint simd_mode:2; 1333 GLuint pad0:1; 1334 GLuint header_present:1; 1335 GLuint response_length:5; 1336 GLuint msg_length:4; 1337 GLuint pad1:2; 1338 GLuint end_of_thread:1; 1339 } sampler_gen5; 1340 1341 struct { 1342 GLuint binding_table_index:8; 1343 GLuint sampler:4; 1344 GLuint msg_type:5; 1345 GLuint simd_mode:2; 1346 GLuint header_present:1; 1347 GLuint response_length:5; 1348 GLuint msg_length:4; 1349 GLuint pad1:2; 1350 GLuint end_of_thread:1; 1351 } sampler_gen7; 1352 1353 struct brw_urb_immediate urb; 1354 1355 struct { 1356 GLuint opcode:4; 1357 GLuint offset:6; 1358 GLuint swizzle_control:2; 1359 GLuint pad:1; 1360 GLuint allocate:1; 1361 GLuint used:1; 1362 GLuint complete:1; 1363 GLuint pad0:3; 1364 GLuint header_present:1; 1365 GLuint response_length:5; 1366 GLuint msg_length:4; 1367 GLuint pad1:2; 1368 GLuint end_of_thread:1; 1369 } urb_gen5; 1370 1371 struct { 1372 GLuint opcode:3; 1373 GLuint offset:11; 1374 GLuint swizzle_control:1; 1375 GLuint complete:1; 1376 GLuint per_slot_offset:1; 1377 GLuint pad0:2; 1378 GLuint header_present:1; 1379 GLuint response_length:5; 1380 GLuint msg_length:4; 1381 GLuint pad1:2; 1382 GLuint end_of_thread:1; 1383 } urb_gen7; 1384 1385 /** 965 PRM, Volume 4, Section 5.10.1.1: Message Descriptor */ 1386 struct { 1387 GLuint binding_table_index:8; 1388 GLuint msg_control:4; 1389 GLuint msg_type:2; 1390 GLuint target_cache:2; 1391 GLuint response_length:4; 1392 GLuint msg_length:4; 1393 GLuint msg_target:4; 1394 GLuint pad1:3; 1395 GLuint end_of_thread:1; 1396 } dp_read; 1397 1398 /** G45 PRM, Volume 4, Section 5.10.1.1.2 */ 1399 struct { 1400 GLuint binding_table_index:8; 1401 GLuint msg_control:3; 1402 GLuint msg_type:3; 1403 GLuint target_cache:2; 1404 GLuint response_length:4; 1405 GLuint msg_length:4; 1406 GLuint msg_target:4; 1407 GLuint pad1:3; 1408 GLuint end_of_thread:1; 1409 } dp_read_g4x; 1410 1411 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */ 1412 struct { 1413 GLuint binding_table_index:8; 1414 GLuint msg_control:3; 1415 GLuint msg_type:3; 1416 GLuint target_cache:2; 1417 GLuint pad0:3; 1418 GLuint header_present:1; 1419 GLuint response_length:5; 1420 GLuint msg_length:4; 1421 GLuint pad1:2; 1422 GLuint end_of_thread:1; 1423 } dp_read_gen5; 1424 1425 /** G45 PRM, Volume 4, Section 5.10.1.1.2. For both Gen4 and G45. */ 1426 struct { 1427 GLuint binding_table_index:8; 1428 GLuint msg_control:3; 1429 GLuint last_render_target:1; 1430 GLuint msg_type:3; 1431 GLuint send_commit_msg:1; 1432 GLuint response_length:4; 1433 GLuint msg_length:4; 1434 GLuint msg_target:4; 1435 GLuint pad1:3; 1436 GLuint end_of_thread:1; 1437 } dp_write; 1438 1439 /** Ironlake PRM, Volume 4 Part 1, Section 5.10.2.1.2. */ 1440 struct { 1441 GLuint binding_table_index:8; 1442 GLuint msg_control:3; 1443 GLuint last_render_target:1; 1444 GLuint msg_type:3; 1445 GLuint send_commit_msg:1; 1446 GLuint pad0:3; 1447 GLuint header_present:1; 1448 GLuint response_length:5; 1449 GLuint msg_length:4; 1450 GLuint pad1:2; 1451 GLuint end_of_thread:1; 1452 } dp_write_gen5; 1453 1454 /** 1455 * Message for the Sandybridge Sampler Cache or Constant Cache Data Port. 1456 * 1457 * See the Sandybridge PRM, Volume 4 Part 1, Section 3.9.2.1.1. 1458 **/ 1459 struct { 1460 GLuint binding_table_index:8; 1461 GLuint msg_control:5; 1462 GLuint msg_type:3; 1463 GLuint pad0:3; 1464 GLuint header_present:1; 1465 GLuint response_length:5; 1466 GLuint msg_length:4; 1467 GLuint pad1:2; 1468 GLuint end_of_thread:1; 1469 } gen6_dp_sampler_const_cache; 1470 1471 /** 1472 * Message for the Sandybridge Render Cache Data Port. 1473 * 1474 * Most fields are defined in the Sandybridge PRM, Volume 4 Part 1, 1475 * Section 3.9.2.1.1: Message Descriptor. 1476 * 1477 * "Slot Group Select" and "Last Render Target" are part of the 1478 * 5-bit message control for Render Target Write messages. See 1479 * Section 3.9.9.2.1 of the same volume. 1480 */ 1481 struct { 1482 GLuint binding_table_index:8; 1483 GLuint msg_control:3; 1484 GLuint slot_group_select:1; 1485 GLuint last_render_target:1; 1486 GLuint msg_type:4; 1487 GLuint send_commit_msg:1; 1488 GLuint pad0:1; 1489 GLuint header_present:1; 1490 GLuint response_length:5; 1491 GLuint msg_length:4; 1492 GLuint pad1:2; 1493 GLuint end_of_thread:1; 1494 } gen6_dp; 1495 1496 /** 1497 * Message for any of the Gen7 Data Port caches. 1498 * 1499 * Most fields are defined in BSpec volume 5c.2 Data Port / Messages / 1500 * Data Port Messages / Message Descriptor. Once again, "Slot Group 1501 * Select" and "Last Render Target" are part of the 6-bit message 1502 * control for Render Target Writes. 1503 */ 1504 struct { 1505 GLuint binding_table_index:8; 1506 GLuint msg_control:3; 1507 GLuint slot_group_select:1; 1508 GLuint last_render_target:1; 1509 GLuint msg_control_pad:1; 1510 GLuint msg_type:4; 1511 GLuint pad1:1; 1512 GLuint header_present:1; 1513 GLuint response_length:5; 1514 GLuint msg_length:4; 1515 GLuint pad2:2; 1516 GLuint end_of_thread:1; 1517 } gen7_dp; 1518 /** @} */ 1519 1520 struct { 1521 GLuint src1_subreg_nr_high:1; 1522 GLuint src1_reg_nr:8; 1523 GLuint pad0:1; 1524 GLuint src2_rep_ctrl:1; 1525 GLuint src2_swizzle:8; 1526 GLuint src2_subreg_nr:3; 1527 GLuint src2_reg_nr:8; 1528 GLuint pad1:2; 1529 } da3src; 1530 1531 GLint d; 1532 GLuint ud; 1533 float f; 1534 } bits3; 1535 }; 1536 1537 1538 #endif 1539
