1 /* Disassembler interface for targets using CGEN. -*- C -*- 2 CGEN: Cpu tools GENerator 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 - the resultant file is machine generated, cgen-dis.in isn't 6 7 Copyright (C) 1996-2014 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "libiberty.h" 35 #include "xstormy16-desc.h" 36 #include "xstormy16-opc.h" 37 #include "opintl.h" 38 39 /* Default text to print if an instruction isn't recognized. */ 40 #define UNKNOWN_INSN_MSG _("*unknown*") 41 42 static void print_normal 43 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 44 static void print_address 45 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 46 static void print_keyword 47 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 48 static void print_insn_normal 49 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 50 static int print_insn 51 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 52 static int default_print_insn 53 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 54 static int read_insn 55 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 56 unsigned long *); 57 58 /* -- disassembler routines inserted here. */ 60 61 62 void xstormy16_cgen_print_operand 63 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 64 65 /* Main entry point for printing operands. 66 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 67 of dis-asm.h on cgen.h. 68 69 This function is basically just a big switch statement. Earlier versions 70 used tables to look up the function to use, but 71 - if the table contains both assembler and disassembler functions then 72 the disassembler contains much of the assembler and vice-versa, 73 - there's a lot of inlining possibilities as things grow, 74 - using a switch statement avoids the function call overhead. 75 76 This function could be moved into `print_insn_normal', but keeping it 77 separate makes clear the interface between `print_insn_normal' and each of 78 the handlers. */ 79 80 void 81 xstormy16_cgen_print_operand (CGEN_CPU_DESC cd, 82 int opindex, 83 void * xinfo, 84 CGEN_FIELDS *fields, 85 void const *attrs ATTRIBUTE_UNUSED, 86 bfd_vma pc, 87 int length) 88 { 89 disassemble_info *info = (disassemble_info *) xinfo; 90 91 switch (opindex) 92 { 93 case XSTORMY16_OPERAND_RB : 94 print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0); 95 break; 96 case XSTORMY16_OPERAND_RBJ : 97 print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0); 98 break; 99 case XSTORMY16_OPERAND_RD : 100 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0); 101 break; 102 case XSTORMY16_OPERAND_RDM : 103 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0); 104 break; 105 case XSTORMY16_OPERAND_RM : 106 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0); 107 break; 108 case XSTORMY16_OPERAND_RS : 109 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0); 110 break; 111 case XSTORMY16_OPERAND_ABS24 : 112 print_normal (cd, info, fields->f_abs24, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 113 break; 114 case XSTORMY16_OPERAND_BCOND2 : 115 print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0); 116 break; 117 case XSTORMY16_OPERAND_BCOND5 : 118 print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0); 119 break; 120 case XSTORMY16_OPERAND_HMEM8 : 121 print_normal (cd, info, fields->f_hmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 122 break; 123 case XSTORMY16_OPERAND_IMM12 : 124 print_normal (cd, info, fields->f_imm12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 125 break; 126 case XSTORMY16_OPERAND_IMM16 : 127 print_normal (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); 128 break; 129 case XSTORMY16_OPERAND_IMM2 : 130 print_normal (cd, info, fields->f_imm2, 0, pc, length); 131 break; 132 case XSTORMY16_OPERAND_IMM3 : 133 print_normal (cd, info, fields->f_imm3, 0, pc, length); 134 break; 135 case XSTORMY16_OPERAND_IMM3B : 136 print_normal (cd, info, fields->f_imm3b, 0, pc, length); 137 break; 138 case XSTORMY16_OPERAND_IMM4 : 139 print_normal (cd, info, fields->f_imm4, 0, pc, length); 140 break; 141 case XSTORMY16_OPERAND_IMM8 : 142 print_normal (cd, info, fields->f_imm8, 0, pc, length); 143 break; 144 case XSTORMY16_OPERAND_IMM8SMALL : 145 print_normal (cd, info, fields->f_imm8, 0, pc, length); 146 break; 147 case XSTORMY16_OPERAND_LMEM8 : 148 print_normal (cd, info, fields->f_lmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 149 break; 150 case XSTORMY16_OPERAND_REL12 : 151 print_normal (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 152 break; 153 case XSTORMY16_OPERAND_REL12A : 154 print_normal (cd, info, fields->f_rel12a, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 155 break; 156 case XSTORMY16_OPERAND_REL8_2 : 157 print_normal (cd, info, fields->f_rel8_2, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 158 break; 159 case XSTORMY16_OPERAND_REL8_4 : 160 print_normal (cd, info, fields->f_rel8_4, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 161 break; 162 case XSTORMY16_OPERAND_WS2 : 163 print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0); 164 break; 165 166 default : 167 /* xgettext:c-format */ 168 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 169 opindex); 170 abort (); 171 } 172 } 173 174 cgen_print_fn * const xstormy16_cgen_print_handlers[] = 175 { 176 print_insn_normal, 177 }; 178 179 180 void 181 xstormy16_cgen_init_dis (CGEN_CPU_DESC cd) 182 { 183 xstormy16_cgen_init_opcode_table (cd); 184 xstormy16_cgen_init_ibld_table (cd); 185 cd->print_handlers = & xstormy16_cgen_print_handlers[0]; 186 cd->print_operand = xstormy16_cgen_print_operand; 187 } 188 189 190 /* Default print handler. */ 192 193 static void 194 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 195 void *dis_info, 196 long value, 197 unsigned int attrs, 198 bfd_vma pc ATTRIBUTE_UNUSED, 199 int length ATTRIBUTE_UNUSED) 200 { 201 disassemble_info *info = (disassemble_info *) dis_info; 202 203 /* Print the operand as directed by the attributes. */ 204 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 205 ; /* nothing to do */ 206 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 207 (*info->fprintf_func) (info->stream, "%ld", value); 208 else 209 (*info->fprintf_func) (info->stream, "0x%lx", value); 210 } 211 212 /* Default address handler. */ 213 214 static void 215 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 216 void *dis_info, 217 bfd_vma value, 218 unsigned int attrs, 219 bfd_vma pc ATTRIBUTE_UNUSED, 220 int length ATTRIBUTE_UNUSED) 221 { 222 disassemble_info *info = (disassemble_info *) dis_info; 223 224 /* Print the operand as directed by the attributes. */ 225 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 226 ; /* Nothing to do. */ 227 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 228 (*info->print_address_func) (value, info); 229 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 230 (*info->print_address_func) (value, info); 231 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 232 (*info->fprintf_func) (info->stream, "%ld", (long) value); 233 else 234 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 235 } 236 237 /* Keyword print handler. */ 238 239 static void 240 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 241 void *dis_info, 242 CGEN_KEYWORD *keyword_table, 243 long value, 244 unsigned int attrs ATTRIBUTE_UNUSED) 245 { 246 disassemble_info *info = (disassemble_info *) dis_info; 247 const CGEN_KEYWORD_ENTRY *ke; 248 249 ke = cgen_keyword_lookup_value (keyword_table, value); 250 if (ke != NULL) 251 (*info->fprintf_func) (info->stream, "%s", ke->name); 252 else 253 (*info->fprintf_func) (info->stream, "???"); 254 } 255 256 /* Default insn printer. 258 259 DIS_INFO is defined as `void *' so the disassembler needn't know anything 260 about disassemble_info. */ 261 262 static void 263 print_insn_normal (CGEN_CPU_DESC cd, 264 void *dis_info, 265 const CGEN_INSN *insn, 266 CGEN_FIELDS *fields, 267 bfd_vma pc, 268 int length) 269 { 270 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 271 disassemble_info *info = (disassemble_info *) dis_info; 272 const CGEN_SYNTAX_CHAR_TYPE *syn; 273 274 CGEN_INIT_PRINT (cd); 275 276 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 277 { 278 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 279 { 280 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 281 continue; 282 } 283 if (CGEN_SYNTAX_CHAR_P (*syn)) 284 { 285 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 286 continue; 287 } 288 289 /* We have an operand. */ 290 xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 291 fields, CGEN_INSN_ATTRS (insn), pc, length); 292 } 293 } 294 295 /* Subroutine of print_insn. Reads an insn into the given buffers and updates 297 the extract info. 298 Returns 0 if all is well, non-zero otherwise. */ 299 300 static int 301 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 302 bfd_vma pc, 303 disassemble_info *info, 304 bfd_byte *buf, 305 int buflen, 306 CGEN_EXTRACT_INFO *ex_info, 307 unsigned long *insn_value) 308 { 309 int status = (*info->read_memory_func) (pc, buf, buflen, info); 310 311 if (status != 0) 312 { 313 (*info->memory_error_func) (status, pc, info); 314 return -1; 315 } 316 317 ex_info->dis_info = info; 318 ex_info->valid = (1 << buflen) - 1; 319 ex_info->insn_bytes = buf; 320 321 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 322 return 0; 323 } 324 325 /* Utility to print an insn. 326 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 327 The result is the size of the insn in bytes or zero for an unknown insn 328 or -1 if an error occurs fetching data (memory_error_func will have 329 been called). */ 330 331 static int 332 print_insn (CGEN_CPU_DESC cd, 333 bfd_vma pc, 334 disassemble_info *info, 335 bfd_byte *buf, 336 unsigned int buflen) 337 { 338 CGEN_INSN_INT insn_value; 339 const CGEN_INSN_LIST *insn_list; 340 CGEN_EXTRACT_INFO ex_info; 341 int basesize; 342 343 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 344 basesize = cd->base_insn_bitsize < buflen * 8 ? 345 cd->base_insn_bitsize : buflen * 8; 346 insn_value = cgen_get_insn_value (cd, buf, basesize); 347 348 349 /* Fill in ex_info fields like read_insn would. Don't actually call 350 read_insn, since the incoming buffer is already read (and possibly 351 modified a la m32r). */ 352 ex_info.valid = (1 << buflen) - 1; 353 ex_info.dis_info = info; 354 ex_info.insn_bytes = buf; 355 356 /* The instructions are stored in hash lists. 357 Pick the first one and keep trying until we find the right one. */ 358 359 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 360 while (insn_list != NULL) 361 { 362 const CGEN_INSN *insn = insn_list->insn; 363 CGEN_FIELDS fields; 364 int length; 365 unsigned long insn_value_cropped; 366 367 #ifdef CGEN_VALIDATE_INSN_SUPPORTED 368 /* Not needed as insn shouldn't be in hash lists if not supported. */ 369 /* Supported by this cpu? */ 370 if (! xstormy16_cgen_insn_supported (cd, insn)) 371 { 372 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 373 continue; 374 } 375 #endif 376 377 /* Basic bit mask must be correct. */ 378 /* ??? May wish to allow target to defer this check until the extract 379 handler. */ 380 381 /* Base size may exceed this instruction's size. Extract the 382 relevant part from the buffer. */ 383 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 384 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 385 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 386 info->endian == BFD_ENDIAN_BIG); 387 else 388 insn_value_cropped = insn_value; 389 390 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 391 == CGEN_INSN_BASE_VALUE (insn)) 392 { 393 /* Printing is handled in two passes. The first pass parses the 394 machine insn and extracts the fields. The second pass prints 395 them. */ 396 397 /* Make sure the entire insn is loaded into insn_value, if it 398 can fit. */ 399 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 400 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 401 { 402 unsigned long full_insn_value; 403 int rc = read_insn (cd, pc, info, buf, 404 CGEN_INSN_BITSIZE (insn) / 8, 405 & ex_info, & full_insn_value); 406 if (rc != 0) 407 return rc; 408 length = CGEN_EXTRACT_FN (cd, insn) 409 (cd, insn, &ex_info, full_insn_value, &fields, pc); 410 } 411 else 412 length = CGEN_EXTRACT_FN (cd, insn) 413 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 414 415 /* Length < 0 -> error. */ 416 if (length < 0) 417 return length; 418 if (length > 0) 419 { 420 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 421 /* Length is in bits, result is in bytes. */ 422 return length / 8; 423 } 424 } 425 426 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 427 } 428 429 return 0; 430 } 431 432 /* Default value for CGEN_PRINT_INSN. 433 The result is the size of the insn in bytes or zero for an unknown insn 434 or -1 if an error occured fetching bytes. */ 435 436 #ifndef CGEN_PRINT_INSN 437 #define CGEN_PRINT_INSN default_print_insn 438 #endif 439 440 static int 441 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 442 { 443 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 444 int buflen; 445 int status; 446 447 /* Attempt to read the base part of the insn. */ 448 buflen = cd->base_insn_bitsize / 8; 449 status = (*info->read_memory_func) (pc, buf, buflen, info); 450 451 /* Try again with the minimum part, if min < base. */ 452 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 453 { 454 buflen = cd->min_insn_bitsize / 8; 455 status = (*info->read_memory_func) (pc, buf, buflen, info); 456 } 457 458 if (status != 0) 459 { 460 (*info->memory_error_func) (status, pc, info); 461 return -1; 462 } 463 464 return print_insn (cd, pc, info, buf, buflen); 465 } 466 467 /* Main entry point. 468 Print one instruction from PC on INFO->STREAM. 469 Return the size of the instruction (in bytes). */ 470 471 typedef struct cpu_desc_list 472 { 473 struct cpu_desc_list *next; 474 CGEN_BITSET *isa; 475 int mach; 476 int endian; 477 CGEN_CPU_DESC cd; 478 } cpu_desc_list; 479 480 int 481 print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) 482 { 483 static cpu_desc_list *cd_list = 0; 484 cpu_desc_list *cl = 0; 485 static CGEN_CPU_DESC cd = 0; 486 static CGEN_BITSET *prev_isa; 487 static int prev_mach; 488 static int prev_endian; 489 int length; 490 CGEN_BITSET *isa; 491 int mach; 492 int endian = (info->endian == BFD_ENDIAN_BIG 493 ? CGEN_ENDIAN_BIG 494 : CGEN_ENDIAN_LITTLE); 495 enum bfd_architecture arch; 496 497 /* ??? gdb will set mach but leave the architecture as "unknown" */ 498 #ifndef CGEN_BFD_ARCH 499 #define CGEN_BFD_ARCH bfd_arch_xstormy16 500 #endif 501 arch = info->arch; 502 if (arch == bfd_arch_unknown) 503 arch = CGEN_BFD_ARCH; 504 505 /* There's no standard way to compute the machine or isa number 506 so we leave it to the target. */ 507 #ifdef CGEN_COMPUTE_MACH 508 mach = CGEN_COMPUTE_MACH (info); 509 #else 510 mach = info->mach; 511 #endif 512 513 #ifdef CGEN_COMPUTE_ISA 514 { 515 static CGEN_BITSET *permanent_isa; 516 517 if (!permanent_isa) 518 permanent_isa = cgen_bitset_create (MAX_ISAS); 519 isa = permanent_isa; 520 cgen_bitset_clear (isa); 521 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 522 } 523 #else 524 isa = info->insn_sets; 525 #endif 526 527 /* If we've switched cpu's, try to find a handle we've used before */ 528 if (cd 529 && (cgen_bitset_compare (isa, prev_isa) != 0 530 || mach != prev_mach 531 || endian != prev_endian)) 532 { 533 cd = 0; 534 for (cl = cd_list; cl; cl = cl->next) 535 { 536 if (cgen_bitset_compare (cl->isa, isa) == 0 && 537 cl->mach == mach && 538 cl->endian == endian) 539 { 540 cd = cl->cd; 541 prev_isa = cd->isas; 542 break; 543 } 544 } 545 } 546 547 /* If we haven't initialized yet, initialize the opcode table. */ 548 if (! cd) 549 { 550 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 551 const char *mach_name; 552 553 if (!arch_type) 554 abort (); 555 mach_name = arch_type->printable_name; 556 557 prev_isa = cgen_bitset_copy (isa); 558 prev_mach = mach; 559 prev_endian = endian; 560 cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 561 CGEN_CPU_OPEN_BFDMACH, mach_name, 562 CGEN_CPU_OPEN_ENDIAN, prev_endian, 563 CGEN_CPU_OPEN_END); 564 if (!cd) 565 abort (); 566 567 /* Save this away for future reference. */ 568 cl = xmalloc (sizeof (struct cpu_desc_list)); 569 cl->cd = cd; 570 cl->isa = prev_isa; 571 cl->mach = mach; 572 cl->endian = endian; 573 cl->next = cd_list; 574 cd_list = cl; 575 576 xstormy16_cgen_init_dis (cd); 577 } 578 579 /* We try to have as much common code as possible. 580 But at this point some targets need to take over. */ 581 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 582 but if not possible try to move this hook elsewhere rather than 583 have two hooks. */ 584 length = CGEN_PRINT_INSN (cd, pc, info); 585 if (length > 0) 586 return length; 587 if (length < 0) 588 return -1; 589 590 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 591 return cd->default_insn_bitsize / 8; 592 } 593
