1 /* 2 * Copyright 2010 Jerome Glisse <glisse (at) freedesktop.org> 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Jerome Glisse 25 */ 26 #ifndef R600_PIPE_H 27 #define R600_PIPE_H 28 29 #include "util/u_blitter.h" 30 #include "util/u_slab.h" 31 #include "r600.h" 32 #include "r600_llvm.h" 33 #include "r600_public.h" 34 #include "r600_shader.h" 35 #include "r600_resource.h" 36 #include "evergreen_compute.h" 37 38 #define R600_MAX_CONST_BUFFERS 2 39 #define R600_MAX_CONST_BUFFER_SIZE 4096 40 41 #ifdef PIPE_ARCH_BIG_ENDIAN 42 #define R600_BIG_ENDIAN 1 43 #else 44 #define R600_BIG_ENDIAN 0 45 #endif 46 47 enum r600_atom_flags { 48 /* When set, atoms are added at the beginning of the dirty list 49 * instead of the end. */ 50 EMIT_EARLY = (1 << 0) 51 }; 52 53 /* This encapsulates a state or an operation which can emitted into the GPU 54 * command stream. It's not limited to states only, it can be used for anything 55 * that wants to write commands into the CS (e.g. cache flushes). */ 56 struct r600_atom { 57 void (*emit)(struct r600_context *ctx, struct r600_atom *state); 58 59 unsigned num_dw; 60 enum r600_atom_flags flags; 61 bool dirty; 62 63 struct list_head head; 64 }; 65 66 /* This is an atom containing GPU commands that never change. 67 * This is supposed to be copied directly into the CS. */ 68 struct r600_command_buffer { 69 struct r600_atom atom; 70 uint32_t *buf; 71 unsigned max_num_dw; 72 unsigned pkt_flags; 73 }; 74 75 struct r600_surface_sync_cmd { 76 struct r600_atom atom; 77 unsigned flush_flags; /* CP_COHER_CNTL */ 78 }; 79 80 struct r600_db_misc_state { 81 struct r600_atom atom; 82 bool occlusion_query_enabled; 83 bool flush_depthstencil_through_cb; 84 bool copy_depth, copy_stencil; 85 unsigned copy_sample; 86 unsigned log_samples; 87 }; 88 89 struct r600_cb_misc_state { 90 struct r600_atom atom; 91 unsigned cb_color_control; /* this comes from blend state */ 92 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */ 93 unsigned nr_cbufs; 94 unsigned nr_ps_color_outputs; 95 bool multiwrite; 96 bool dual_src_blend; 97 }; 98 99 struct r600_alphatest_state { 100 struct r600_atom atom; 101 unsigned sx_alpha_test_control; /* this comes from dsa state */ 102 unsigned sx_alpha_ref; /* this comes from dsa state */ 103 bool bypass; 104 bool cb0_export_16bpc; /* from set_framebuffer_state */ 105 }; 106 107 struct r600_cs_shader_state { 108 struct r600_atom atom; 109 struct r600_pipe_compute *shader; 110 }; 111 112 struct r600_sample_mask { 113 struct r600_atom atom; 114 uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */ 115 }; 116 117 enum r600_pipe_state_id { 118 R600_PIPE_STATE_BLEND = 0, 119 R600_PIPE_STATE_BLEND_COLOR, 120 R600_PIPE_STATE_CONFIG, 121 R600_PIPE_STATE_SEAMLESS_CUBEMAP, 122 R600_PIPE_STATE_CLIP, 123 R600_PIPE_STATE_SCISSOR, 124 R600_PIPE_STATE_VIEWPORT, 125 R600_PIPE_STATE_RASTERIZER, 126 R600_PIPE_STATE_VGT, 127 R600_PIPE_STATE_FRAMEBUFFER, 128 R600_PIPE_STATE_DSA, 129 R600_PIPE_STATE_STENCIL_REF, 130 R600_PIPE_STATE_PS_SHADER, 131 R600_PIPE_STATE_VS_SHADER, 132 R600_PIPE_STATE_CONSTANT, 133 R600_PIPE_STATE_SAMPLER, 134 R600_PIPE_STATE_RESOURCE, 135 R600_PIPE_STATE_POLYGON_OFFSET, 136 R600_PIPE_STATE_FETCH_SHADER, 137 R600_PIPE_STATE_SPI, 138 R600_PIPE_NSTATES 139 }; 140 141 struct compute_memory_pool; 142 void compute_memory_pool_delete(struct compute_memory_pool* pool); 143 struct compute_memory_pool* compute_memory_pool_new( 144 struct r600_screen *rscreen); 145 146 struct r600_pipe_fences { 147 struct r600_resource *bo; 148 unsigned *data; 149 unsigned next_index; 150 /* linked list of preallocated blocks */ 151 struct list_head blocks; 152 /* linked list of freed fences */ 153 struct list_head pool; 154 pipe_mutex mutex; 155 }; 156 157 struct r600_screen { 158 struct pipe_screen screen; 159 struct radeon_winsys *ws; 160 unsigned family; 161 enum chip_class chip_class; 162 struct radeon_info info; 163 bool has_streamout; 164 struct r600_tiling_info tiling_info; 165 struct r600_pipe_fences fences; 166 167 /*for compute global memory binding, we allocate stuff here, instead of 168 * buffers. 169 * XXX: Not sure if this is the best place for global_pool. Also, 170 * it's not thread safe, so it won't work with multiple contexts. */ 171 struct compute_memory_pool *global_pool; 172 }; 173 174 struct r600_pipe_sampler_view { 175 struct pipe_sampler_view base; 176 struct r600_resource *tex_resource; 177 uint32_t tex_resource_words[8]; 178 }; 179 180 struct r600_pipe_rasterizer { 181 struct r600_pipe_state rstate; 182 boolean flatshade; 183 boolean two_side; 184 unsigned sprite_coord_enable; 185 unsigned clip_plane_enable; 186 unsigned pa_sc_line_stipple; 187 unsigned pa_cl_clip_cntl; 188 float offset_units; 189 float offset_scale; 190 bool scissor_enable; 191 bool multisample_enable; 192 }; 193 194 struct r600_pipe_blend { 195 struct r600_pipe_state rstate; 196 unsigned cb_target_mask; 197 unsigned cb_color_control; 198 bool dual_src_blend; 199 bool alpha_to_one; 200 }; 201 202 struct r600_pipe_dsa { 203 struct r600_pipe_state rstate; 204 unsigned alpha_ref; 205 ubyte valuemask[2]; 206 ubyte writemask[2]; 207 unsigned sx_alpha_test_control; 208 }; 209 210 struct r600_vertex_element 211 { 212 unsigned count; 213 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS]; 214 struct r600_resource *fetch_shader; 215 unsigned fs_size; 216 struct r600_pipe_state rstate; 217 }; 218 219 struct r600_pipe_shader; 220 221 struct r600_pipe_shader_selector { 222 struct r600_pipe_shader *current; 223 224 struct tgsi_token *tokens; 225 struct pipe_stream_output_info so; 226 227 unsigned num_shaders; 228 229 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */ 230 unsigned type; 231 232 unsigned nr_ps_max_color_exports; 233 }; 234 235 struct r600_pipe_shader { 236 struct r600_pipe_shader_selector *selector; 237 struct r600_pipe_shader *next_variant; 238 struct r600_shader shader; 239 struct r600_pipe_state rstate; 240 struct r600_resource *bo; 241 struct r600_resource *bo_fetch; 242 struct r600_vertex_element vertex_elements; 243 unsigned sprite_coord_enable; 244 unsigned flatshade; 245 unsigned pa_cl_vs_out_cntl; 246 unsigned nr_ps_color_outputs; 247 unsigned key; 248 unsigned db_shader_control; 249 unsigned ps_depth_export; 250 }; 251 252 struct r600_pipe_sampler_state { 253 uint32_t tex_sampler_words[3]; 254 uint32_t border_color[4]; 255 bool border_color_use; 256 bool seamless_cube_map; 257 }; 258 259 /* needed for blitter save */ 260 #define NUM_TEX_UNITS 16 261 262 struct r600_seamless_cube_map { 263 struct r600_atom atom; 264 bool enabled; 265 }; 266 267 struct r600_samplerview_state { 268 struct r600_atom atom; 269 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS]; 270 uint32_t enabled_mask; 271 uint32_t dirty_mask; 272 uint32_t compressed_depthtex_mask; /* which textures are depth */ 273 uint32_t compressed_colortex_mask; 274 }; 275 276 struct r600_textures_info { 277 struct r600_samplerview_state views; 278 struct r600_atom atom_sampler; 279 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS]; 280 unsigned n_samplers; 281 bool is_array_sampler[NUM_TEX_UNITS]; 282 }; 283 284 struct r600_fence { 285 struct pipe_reference reference; 286 unsigned index; /* in the shared bo */ 287 struct r600_resource *sleep_bo; 288 struct list_head head; 289 }; 290 291 #define FENCE_BLOCK_SIZE 16 292 293 struct r600_fence_block { 294 struct r600_fence fences[FENCE_BLOCK_SIZE]; 295 struct list_head head; 296 }; 297 298 #define R600_CONSTANT_ARRAY_SIZE 256 299 #define R600_RESOURCE_ARRAY_SIZE 160 300 301 struct r600_stencil_ref 302 { 303 ubyte ref_value[2]; 304 ubyte valuemask[2]; 305 ubyte writemask[2]; 306 }; 307 308 struct r600_constbuf_state 309 { 310 struct r600_atom atom; 311 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS]; 312 uint32_t enabled_mask; 313 uint32_t dirty_mask; 314 }; 315 316 struct r600_vertexbuf_state 317 { 318 struct r600_atom atom; 319 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS]; 320 uint32_t enabled_mask; /* non-NULL buffers */ 321 uint32_t dirty_mask; 322 }; 323 324 struct r600_context { 325 struct pipe_context context; 326 struct blitter_context *blitter; 327 enum radeon_family family; 328 enum chip_class chip_class; 329 boolean has_vertex_cache; 330 unsigned r6xx_num_clause_temp_gprs; 331 void *custom_dsa_flush; 332 void *custom_blend_resolve; 333 void *custom_blend_decompress; 334 335 struct r600_screen *screen; 336 struct radeon_winsys *ws; 337 struct r600_pipe_state *states[R600_PIPE_NSTATES]; 338 struct r600_vertex_element *vertex_elements; 339 struct pipe_framebuffer_state framebuffer; 340 unsigned compressed_cb_mask; 341 unsigned compute_cb_target_mask; 342 unsigned db_shader_control; 343 unsigned pa_sc_line_stipple; 344 unsigned pa_cl_clip_cntl; 345 /* for saving when using blitter */ 346 struct pipe_stencil_ref stencil_ref; 347 struct pipe_viewport_state viewport; 348 struct pipe_clip_state clip; 349 struct r600_pipe_shader_selector *ps_shader; 350 struct r600_pipe_shader_selector *vs_shader; 351 struct r600_pipe_rasterizer *rasterizer; 352 struct r600_pipe_state vgt; 353 struct r600_pipe_state spi; 354 struct pipe_query *current_render_cond; 355 unsigned current_render_cond_mode; 356 struct pipe_query *saved_render_cond; 357 unsigned saved_render_cond_mode; 358 /* shader information */ 359 boolean two_side; 360 boolean spi_dirty; 361 unsigned sprite_coord_enable; 362 boolean flatshade; 363 boolean export_16bpc; 364 unsigned nr_cbufs; 365 bool alpha_to_one; 366 bool multisample_enable; 367 bool cb0_is_integer; 368 369 struct u_upload_mgr *uploader; 370 struct util_slab_mempool pool_transfers; 371 372 unsigned default_ps_gprs, default_vs_gprs; 373 374 /* current unaccounted memory usage */ 375 uint64_t vram; 376 uint64_t gtt; 377 378 /* States based on r600_atom. */ 379 struct list_head dirty_states; 380 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */ 381 /** Compute specific registers initializations. The start_cs_cmd atom 382 * must be emitted before start_compute_cs_cmd. */ 383 struct r600_command_buffer start_compute_cs_cmd; 384 struct r600_surface_sync_cmd surface_sync_cmd; 385 struct r600_atom r6xx_flush_and_inv_cmd; 386 struct r600_alphatest_state alphatest_state; 387 struct r600_cb_misc_state cb_misc_state; 388 struct r600_db_misc_state db_misc_state; 389 /** Vertex buffers for fetch shaders */ 390 struct r600_vertexbuf_state vertex_buffer_state; 391 /** Vertex buffers for compute shaders */ 392 struct r600_vertexbuf_state cs_vertex_buffer_state; 393 struct r600_constbuf_state vs_constbuf_state; 394 struct r600_constbuf_state ps_constbuf_state; 395 struct r600_textures_info vs_samplers; 396 struct r600_textures_info ps_samplers; 397 struct r600_seamless_cube_map seamless_cube_map; 398 struct r600_cs_shader_state cs_shader_state; 399 struct r600_sample_mask sample_mask; 400 401 /* current external blend state (from state tracker) */ 402 struct r600_pipe_blend *blend; 403 /* state with disabled blending - used internally with blend_override */ 404 struct r600_pipe_blend *no_blend; 405 406 /* 1 - override current blend state with no_blend, 0 - use external state */ 407 unsigned blend_override; 408 409 struct radeon_winsys_cs *cs; 410 411 struct r600_range *range; 412 unsigned nblocks; 413 struct r600_block **blocks; 414 struct list_head dirty; 415 struct list_head enable_list; 416 unsigned pm4_dirty_cdwords; 417 unsigned ctx_pm4_ndwords; 418 419 /* The list of active queries. Only one query of each type can be active. */ 420 int num_occlusion_queries; 421 422 /* Manage queries in two separate groups: 423 * The timer ones and the others (streamout, occlusion). 424 * 425 * We do this because we should only suspend non-timer queries for u_blitter, 426 * and later if the non-timer queries are suspended, the context flush should 427 * only suspend and resume the timer queries. */ 428 struct list_head active_timer_queries; 429 unsigned num_cs_dw_timer_queries_suspend; 430 struct list_head active_nontimer_queries; 431 unsigned num_cs_dw_nontimer_queries_suspend; 432 433 unsigned num_cs_dw_streamout_end; 434 435 unsigned backend_mask; 436 unsigned max_db; /* for OQ */ 437 unsigned flags; 438 boolean predicate_drawing; 439 440 unsigned num_so_targets; 441 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS]; 442 boolean streamout_start; 443 unsigned streamout_append_bitmask; 444 445 /* There is no scissor enable bit on r6xx, so we must use a workaround. 446 * These track the current scissor state. */ 447 bool scissor_enable; 448 struct pipe_scissor_state scissor_state; 449 450 /* With rasterizer discard, there doesn't have to be a pixel shader. 451 * In that case, we bind this one: */ 452 void *dummy_pixel_shader; 453 454 boolean dual_src_blend; 455 456 /* Index buffer. */ 457 struct pipe_index_buffer index_buffer; 458 459 /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware 460 * bug where valid CMASK and FMASK are required to be present to avoid 461 * a hardlock in certain operations but aren't actually used 462 * for anything useful. */ 463 struct r600_resource *dummy_fmask; 464 struct r600_resource *dummy_cmask; 465 }; 466 467 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom) 468 { 469 atom->emit(rctx, atom); 470 atom->dirty = false; 471 if (atom->head.next && atom->head.prev) 472 LIST_DELINIT(&atom->head); 473 } 474 475 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state) 476 { 477 if (!state->dirty) { 478 if (state->flags & EMIT_EARLY) { 479 LIST_ADD(&state->head, &rctx->dirty_states); 480 } else { 481 LIST_ADDTAIL(&state->head, &rctx->dirty_states); 482 } 483 state->dirty = true; 484 } 485 } 486 487 /* evergreen_state.c */ 488 void evergreen_init_common_regs(struct r600_command_buffer *cb, 489 enum chip_class ctx_chip_class, 490 enum radeon_family ctx_family, 491 int ctx_drm_minor); 492 493 void evergreen_init_state_functions(struct r600_context *rctx); 494 void evergreen_init_atom_start_cs(struct r600_context *rctx); 495 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 496 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 497 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 498 void *evergreen_create_db_flush_dsa(struct r600_context *rctx); 499 void *evergreen_create_resolve_blend(struct r600_context *rctx); 500 void *evergreen_create_decompress_blend(struct r600_context *rctx); 501 void evergreen_polygon_offset_update(struct r600_context *rctx); 502 boolean evergreen_is_format_supported(struct pipe_screen *screen, 503 enum pipe_format format, 504 enum pipe_texture_target target, 505 unsigned sample_count, 506 unsigned usage); 507 void evergreen_init_color_surface(struct r600_context *rctx, 508 struct r600_surface *surf); 509 void evergreen_update_dual_export_state(struct r600_context * rctx); 510 511 /* r600_blit.c */ 512 void r600_copy_buffer(struct pipe_context *ctx, struct 513 pipe_resource *dst, unsigned dstx, 514 struct pipe_resource *src, const struct pipe_box *src_box); 515 void r600_init_blit_functions(struct r600_context *rctx); 516 void r600_blit_decompress_depth(struct pipe_context *ctx, 517 struct r600_texture *texture, 518 struct r600_texture *staging, 519 unsigned first_level, unsigned last_level, 520 unsigned first_layer, unsigned last_layer, 521 unsigned first_sample, unsigned last_sample); 522 void r600_decompress_depth_textures(struct r600_context *rctx, 523 struct r600_samplerview_state *textures); 524 void r600_decompress_color_textures(struct r600_context *rctx, 525 struct r600_samplerview_state *textures); 526 527 /* r600_buffer.c */ 528 bool r600_init_resource(struct r600_screen *rscreen, 529 struct r600_resource *res, 530 unsigned size, unsigned alignment, 531 unsigned bind, unsigned usage); 532 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen, 533 const struct pipe_resource *templ, 534 unsigned alignment); 535 536 /* r600_pipe.c */ 537 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence, 538 unsigned flags); 539 540 /* r600_query.c */ 541 void r600_init_query_functions(struct r600_context *rctx); 542 void r600_suspend_nontimer_queries(struct r600_context *ctx); 543 void r600_resume_nontimer_queries(struct r600_context *ctx); 544 void r600_suspend_timer_queries(struct r600_context *ctx); 545 void r600_resume_timer_queries(struct r600_context *ctx); 546 547 /* r600_resource.c */ 548 void r600_init_context_resource_functions(struct r600_context *r600); 549 550 /* r600_shader.c */ 551 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader); 552 #ifdef HAVE_OPENCL 553 int r600_compute_shader_create(struct pipe_context * ctx, 554 LLVMModuleRef mod, struct r600_bytecode * bytecode); 555 #endif 556 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader); 557 558 /* r600_state.c */ 559 void r600_set_scissor_state(struct r600_context *rctx, 560 const struct pipe_scissor_state *state); 561 void r600_init_state_functions(struct r600_context *rctx); 562 void r600_init_atom_start_cs(struct r600_context *rctx); 563 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader); 564 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader); 565 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve); 566 void *r600_create_db_flush_dsa(struct r600_context *rctx); 567 void *r600_create_resolve_blend(struct r600_context *rctx); 568 void *r700_create_resolve_blend(struct r600_context *rctx); 569 void *r600_create_decompress_blend(struct r600_context *rctx); 570 void r600_polygon_offset_update(struct r600_context *rctx); 571 void r600_adjust_gprs(struct r600_context *rctx); 572 boolean r600_is_format_supported(struct pipe_screen *screen, 573 enum pipe_format format, 574 enum pipe_texture_target target, 575 unsigned sample_count, 576 unsigned usage); 577 void r600_update_dual_export_state(struct r600_context * rctx); 578 579 /* r600_texture.c */ 580 void r600_init_screen_texture_functions(struct pipe_screen *screen); 581 void r600_init_surface_functions(struct r600_context *r600); 582 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format, 583 const unsigned char *swizzle_view, 584 uint32_t *word4_p, uint32_t *yuv_format_p); 585 unsigned r600_texture_get_offset(struct r600_texture *rtex, 586 unsigned level, unsigned layer); 587 588 /* r600_translate.c */ 589 void r600_translate_index_buffer(struct r600_context *r600, 590 struct pipe_index_buffer *ib, 591 unsigned count); 592 593 /* r600_state_common.c */ 594 void r600_init_atom(struct r600_atom *atom, 595 void (*emit)(struct r600_context *ctx, struct r600_atom *state), 596 unsigned num_dw, enum r600_atom_flags flags); 597 void r600_init_common_atoms(struct r600_context *rctx); 598 unsigned r600_get_cb_flush_flags(struct r600_context *rctx); 599 void r600_texture_barrier(struct pipe_context *ctx); 600 void r600_set_index_buffer(struct pipe_context *ctx, 601 const struct pipe_index_buffer *ib); 602 void r600_vertex_buffers_dirty(struct r600_context *rctx); 603 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count, 604 const struct pipe_vertex_buffer *input); 605 void r600_sampler_views_dirty(struct r600_context *rctx, 606 struct r600_samplerview_state *state); 607 void r600_set_sampler_views(struct pipe_context *pipe, 608 unsigned shader, 609 unsigned start, 610 unsigned count, 611 struct pipe_sampler_view **views); 612 void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states); 613 void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states); 614 void *r600_create_vertex_elements(struct pipe_context *ctx, 615 unsigned count, 616 const struct pipe_vertex_element *elements); 617 void r600_delete_vertex_element(struct pipe_context *ctx, void *state); 618 void r600_bind_blend_state(struct pipe_context *ctx, void *state); 619 void r600_set_blend_color(struct pipe_context *ctx, 620 const struct pipe_blend_color *state); 621 void r600_bind_dsa_state(struct pipe_context *ctx, void *state); 622 void r600_set_max_scissor(struct r600_context *rctx); 623 void r600_bind_rs_state(struct pipe_context *ctx, void *state); 624 void r600_delete_rs_state(struct pipe_context *ctx, void *state); 625 void r600_sampler_view_destroy(struct pipe_context *ctx, 626 struct pipe_sampler_view *state); 627 void r600_delete_sampler(struct pipe_context *ctx, void *state); 628 void r600_delete_state(struct pipe_context *ctx, void *state); 629 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state); 630 void *r600_create_shader_state_ps(struct pipe_context *ctx, 631 const struct pipe_shader_state *state); 632 void *r600_create_shader_state_vs(struct pipe_context *ctx, 633 const struct pipe_shader_state *state); 634 void r600_bind_ps_shader(struct pipe_context *ctx, void *state); 635 void r600_bind_vs_shader(struct pipe_context *ctx, void *state); 636 void r600_delete_ps_shader(struct pipe_context *ctx, void *state); 637 void r600_delete_vs_shader(struct pipe_context *ctx, void *state); 638 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state); 639 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index, 640 struct pipe_constant_buffer *cb); 641 struct pipe_stream_output_target * 642 r600_create_so_target(struct pipe_context *ctx, 643 struct pipe_resource *buffer, 644 unsigned buffer_offset, 645 unsigned buffer_size); 646 void r600_so_target_destroy(struct pipe_context *ctx, 647 struct pipe_stream_output_target *target); 648 void r600_set_so_targets(struct pipe_context *ctx, 649 unsigned num_targets, 650 struct pipe_stream_output_target **targets, 651 unsigned append_bitmask); 652 void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask); 653 void r600_set_pipe_stencil_ref(struct pipe_context *ctx, 654 const struct pipe_stencil_ref *state); 655 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 656 void r600_draw_rectangle(struct blitter_context *blitter, 657 unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth, 658 enum blitter_attrib_type type, const union pipe_color_union *attrib); 659 uint32_t r600_translate_stencil_op(int s_op); 660 uint32_t r600_translate_fill(uint32_t func); 661 unsigned r600_tex_wrap(unsigned wrap); 662 unsigned r600_tex_filter(unsigned filter); 663 unsigned r600_tex_mipfilter(unsigned filter); 664 unsigned r600_tex_compare(unsigned compare); 665 666 /* 667 * Helpers for building command buffers 668 */ 669 670 #define PKT3_SET_CONFIG_REG 0x68 671 #define PKT3_SET_CONTEXT_REG 0x69 672 #define PKT3_SET_CTL_CONST 0x6F 673 #define PKT3_SET_LOOP_CONST 0x6C 674 675 #define R600_CONFIG_REG_OFFSET 0x08000 676 #define R600_CONTEXT_REG_OFFSET 0x28000 677 #define R600_CTL_CONST_OFFSET 0x3CFF0 678 #define R600_LOOP_CONST_OFFSET 0X0003E200 679 #define EG_LOOP_CONST_OFFSET 0x0003A200 680 681 #define PKT_TYPE_S(x) (((x) & 0x3) << 30) 682 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16) 683 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8) 684 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1) 685 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate)) 686 687 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002 688 689 /*Evergreen Compute packet3*/ 690 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE) 691 692 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value) 693 { 694 cb->buf[cb->atom.num_dw++] = value; 695 } 696 697 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 698 { 699 assert(reg < R600_CONTEXT_REG_OFFSET); 700 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 701 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 702 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 703 } 704 705 /** 706 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 707 * shaders. 708 */ 709 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 710 { 711 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 712 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 713 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags; 714 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 715 } 716 717 /** 718 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 719 * shaders. 720 */ 721 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 722 { 723 assert(reg >= R600_CTL_CONST_OFFSET); 724 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 725 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags; 726 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 727 } 728 729 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 730 { 731 assert(reg >= R600_LOOP_CONST_OFFSET); 732 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 733 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0); 734 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2; 735 } 736 737 /** 738 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute 739 * shaders. 740 */ 741 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num) 742 { 743 assert(reg >= EG_LOOP_CONST_OFFSET); 744 assert(cb->atom.num_dw+2+num <= cb->max_num_dw); 745 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags; 746 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2; 747 } 748 749 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 750 { 751 r600_store_config_reg_seq(cb, reg, 1); 752 r600_store_value(cb, value); 753 } 754 755 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value) 756 { 757 r600_store_context_reg_seq(cb, reg, 1); 758 r600_store_value(cb, value); 759 } 760 761 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 762 { 763 r600_store_ctl_const_seq(cb, reg, 1); 764 r600_store_value(cb, value); 765 } 766 767 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 768 { 769 r600_store_loop_const_seq(cb, reg, 1); 770 r600_store_value(cb, value); 771 } 772 773 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value) 774 { 775 eg_store_loop_const_seq(cb, reg, 1); 776 r600_store_value(cb, value); 777 } 778 779 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags); 780 void r600_release_command_buffer(struct r600_command_buffer *cb); 781 782 /* 783 * Helpers for emitting state into a command stream directly. 784 */ 785 786 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo, 787 enum radeon_bo_usage usage) 788 { 789 assert(usage); 790 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4; 791 } 792 793 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value) 794 { 795 cs->buf[cs->cdw++] = value; 796 } 797 798 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr) 799 { 800 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS); 801 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0])); 802 cs->cdw += num; 803 } 804 805 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 806 { 807 assert(reg < R600_CONTEXT_REG_OFFSET); 808 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 809 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0); 810 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2; 811 } 812 813 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 814 { 815 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET); 816 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 817 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0); 818 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2; 819 } 820 821 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 822 { 823 r600_write_context_reg_seq(cs, reg, num); 824 /* Set the compute bit on the packet header */ 825 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; 826 } 827 828 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) 829 { 830 assert(reg >= R600_CTL_CONST_OFFSET); 831 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS); 832 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0); 833 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2; 834 } 835 836 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 837 { 838 r600_write_config_reg_seq(cs, reg, 1); 839 r600_write_value(cs, value); 840 } 841 842 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 843 { 844 r600_write_context_reg_seq(cs, reg, 1); 845 r600_write_value(cs, value); 846 } 847 848 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 849 { 850 r600_write_compute_context_reg_seq(cs, reg, 1); 851 r600_write_value(cs, value); 852 } 853 854 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) 855 { 856 r600_write_ctl_const_seq(cs, reg, 1); 857 r600_write_value(cs, value); 858 } 859 860 /* 861 * common helpers 862 */ 863 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits) 864 { 865 return value * (1 << frac_bits); 866 } 867 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y)) 868 869 static inline unsigned r600_tex_aniso_filter(unsigned filter) 870 { 871 if (filter <= 1) return 0; 872 if (filter <= 2) return 1; 873 if (filter <= 4) return 2; 874 if (filter <= 8) return 3; 875 /* else */ return 4; 876 } 877 878 /* 12.4 fixed-point */ 879 static INLINE unsigned r600_pack_float_12p4(float x) 880 { 881 return x <= 0 ? 0 : 882 x >= 4096 ? 0xffff : x * 16; 883 } 884 885 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource) 886 { 887 struct r600_screen *rscreen = (struct r600_screen*)screen; 888 struct r600_resource *rresource = (struct r600_resource*)resource; 889 890 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf); 891 } 892 893 static INLINE void r600_context_add_resource_size(struct pipe_context *ctx, struct pipe_resource *r) 894 { 895 struct r600_context *rctx = (struct r600_context *)ctx; 896 struct r600_resource *rr = (struct r600_resource *)r; 897 898 if (r == NULL) { 899 return; 900 } 901 902 /* 903 * The idea is to compute a gross estimate of memory requirement of 904 * each draw call. After each draw call, memory will be precisely 905 * accounted. So the uncertainty is only on the current draw call. 906 * In practice this gave very good estimate (+/- 10% of the target 907 * memory limit). 908 */ 909 if (rr->domains & RADEON_DOMAIN_GTT) { 910 rctx->gtt += rr->buf->size; 911 } 912 if (rr->domains & RADEON_DOMAIN_VRAM) { 913 rctx->vram += rr->buf->size; 914 } 915 } 916 917 #endif 918
