1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright (C) 1989-2014 Free Software Foundation, Inc. 3 This file is part of GAS, the GNU Assembler. 4 5 GAS is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3, or (at your option) 8 any later version. 9 10 GAS is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public 16 License along with GAS; see the file COPYING. If not, write 17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 18 Boston, MA 02110-1301, USA. */ 19 20 #include "as.h" 21 #include "safe-ctype.h" 22 #include "subsegs.h" 23 24 #include "opcode/sparc.h" 25 #include "dw2gencfi.h" 26 27 #ifdef OBJ_ELF 28 #include "elf/sparc.h" 29 #include "dwarf2dbg.h" 30 #endif 31 32 /* Some ancient Sun C compilers would not take such hex constants as 33 unsigned, and would end up sign-extending them to form an offsetT, 34 so use these constants instead. */ 35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 37 38 static int sparc_ip (char *, const struct sparc_opcode **); 39 static int parse_keyword_arg (int (*) (const char *), char **, int *); 40 static int parse_const_expr_arg (char **, int *); 41 static int get_expression (char *); 42 43 /* Default architecture. */ 44 /* ??? The default value should be V8, but sparclite support was added 45 by making it the default. GCC now passes -Asparclite, so maybe sometime in 46 the future we can set this to V8. */ 47 #ifndef DEFAULT_ARCH 48 #define DEFAULT_ARCH "sparclite" 49 #endif 50 static char *default_arch = DEFAULT_ARCH; 51 52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 53 have been set. */ 54 static int default_init_p; 55 56 /* Current architecture. We don't bump up unless necessary. */ 57 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 58 59 /* The maximum architecture level we can bump up to. 60 In a 32 bit environment, don't allow bumping up to v9 by default. 61 The native assembler works this way. The user is required to pass 62 an explicit argument before we'll create v9 object files. However, if 63 we don't see any v9 insns, a v8plus object file is not created. */ 64 static enum sparc_opcode_arch_val max_architecture; 65 66 /* Either 32 or 64, selects file format. */ 67 static int sparc_arch_size; 68 /* Initial (default) value, recorded separately in case a user option 69 changes the value before md_show_usage is called. */ 70 static int default_arch_size; 71 72 #ifdef OBJ_ELF 73 /* The currently selected v9 memory model. Currently only used for 74 ELF. */ 75 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 76 77 #ifndef TE_SOLARIS 78 /* Bitmask of instruction types seen so far, used to populate the 79 GNU attributes section with hwcap information. */ 80 static bfd_uint64_t hwcap_seen; 81 #endif 82 #endif 83 84 static bfd_uint64_t hwcap_allowed; 85 86 static int architecture_requested; 87 static int warn_on_bump; 88 89 /* If warn_on_bump and the needed architecture is higher than this 90 architecture, issue a warning. */ 91 static enum sparc_opcode_arch_val warn_after_architecture; 92 93 /* Non-zero if as should generate error if an undeclared g[23] register 94 has been used in -64. */ 95 static int no_undeclared_regs; 96 97 /* Non-zero if we should try to relax jumps and calls. */ 98 static int sparc_relax; 99 100 /* Non-zero if we are generating PIC code. */ 101 int sparc_pic_code; 102 103 /* Non-zero if we should give an error when misaligned data is seen. */ 104 static int enforce_aligned_data; 105 106 extern int target_big_endian; 107 108 static int target_little_endian_data; 109 110 /* Symbols for global registers on v9. */ 111 static symbolS *globals[8]; 112 113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 114 int sparc_cie_data_alignment; 115 116 /* V9 and 86x have big and little endian data, but instructions are always big 117 endian. The sparclet has bi-endian support but both data and insns have 118 the same endianness. Global `target_big_endian' is used for data. 119 The following macro is used for instructions. */ 120 #ifndef INSN_BIG_ENDIAN 121 #define INSN_BIG_ENDIAN (target_big_endian \ 122 || default_arch_type == sparc86x \ 123 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 124 #endif 125 126 /* Handle of the OPCODE hash table. */ 127 static struct hash_control *op_hash; 128 129 static void s_data1 (void); 130 static void s_seg (int); 131 static void s_proc (int); 132 static void s_reserve (int); 133 static void s_common (int); 134 static void s_empty (int); 135 static void s_uacons (int); 136 static void s_ncons (int); 137 #ifdef OBJ_ELF 138 static void s_register (int); 139 #endif 140 141 const pseudo_typeS md_pseudo_table[] = 142 { 143 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 144 {"common", s_common, 0}, 145 {"empty", s_empty, 0}, 146 {"global", s_globl, 0}, 147 {"half", cons, 2}, 148 {"nword", s_ncons, 0}, 149 {"optim", s_ignore, 0}, 150 {"proc", s_proc, 0}, 151 {"reserve", s_reserve, 0}, 152 {"seg", s_seg, 0}, 153 {"skip", s_space, 0}, 154 {"word", cons, 4}, 155 {"xword", cons, 8}, 156 {"uahalf", s_uacons, 2}, 157 {"uaword", s_uacons, 4}, 158 {"uaxword", s_uacons, 8}, 159 #ifdef OBJ_ELF 160 /* These are specific to sparc/svr4. */ 161 {"2byte", s_uacons, 2}, 162 {"4byte", s_uacons, 4}, 163 {"8byte", s_uacons, 8}, 164 {"register", s_register, 0}, 165 #endif 166 {NULL, 0, 0}, 167 }; 168 169 /* This array holds the chars that always start a comment. If the 170 pre-processor is disabled, these aren't very useful. */ 171 const char comment_chars[] = "!"; /* JF removed '|' from 172 comment_chars. */ 173 174 /* This array holds the chars that only start a comment at the beginning of 175 a line. If the line seems to have the form '# 123 filename' 176 .line and .file directives will appear in the pre-processed output. */ 177 /* Note that input_file.c hand checks for '#' at the beginning of the 178 first line of the input file. This is because the compiler outputs 179 #NO_APP at the beginning of its output. */ 180 /* Also note that comments started like this one will always 181 work if '/' isn't otherwise defined. */ 182 const char line_comment_chars[] = "#"; 183 184 const char line_separator_chars[] = ";"; 185 186 /* Chars that can be used to separate mant from exp in floating point 187 nums. */ 188 const char EXP_CHARS[] = "eE"; 189 190 /* Chars that mean this number is a floating point constant. 191 As in 0f12.456 192 or 0d1.2345e12 */ 193 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 194 195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 196 changed in read.c. Ideally it shouldn't have to know about it at all, 197 but nothing is ideal around here. */ 198 199 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 200 201 struct sparc_it 202 { 203 char *error; 204 unsigned long opcode; 205 struct nlist *nlistp; 206 expressionS exp; 207 expressionS exp2; 208 int pcrel; 209 bfd_reloc_code_real_type reloc; 210 }; 211 212 struct sparc_it the_insn, set_insn; 213 214 static void output_insn (const struct sparc_opcode *, struct sparc_it *); 215 216 /* Table of arguments to -A. 218 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 219 for this use. That table is for opcodes only. This table is for opcodes 220 and file formats. */ 221 222 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, 223 v8plusa, v9, v9a, v9b, v9_64}; 224 225 /* Hardware capability sets, used to keep sparc_arch_table easy to 226 read. */ 227 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD 228 #define HWS_V9 HWS_V8 | HWCAP_POPC 229 #define HWS_VA HWS_V9 | HWCAP_VIS 230 #define HWS_VB HWS_VA | HWCAP_VIS2 231 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT 232 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC 233 #define HWS_VE HWS_VD \ 234 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \ 235 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \ 236 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE 237 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA 238 #define HWS_VM HWS_VV 239 240 #define HWS2_VM \ 241 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \ 242 | HWCAP2_XMPMUL | HWCAP2_XMONT 243 244 static struct sparc_arch { 245 char *name; 246 char *opcode_arch; 247 enum sparc_arch_types arch_type; 248 /* Default word size, as specified during configuration. 249 A value of zero means can't be used to specify default architecture. */ 250 int default_arch_size; 251 /* Allowable arg to -A? */ 252 int user_option_p; 253 int hwcap_allowed; 254 int hwcap2_allowed; 255 } sparc_arch_table[] = { 256 { "v6", "v6", v6, 0, 1, 0, 0 }, 257 { "v7", "v7", v7, 0, 1, 0, 0 }, 258 { "v8", "v8", v8, 32, 1, HWS_V8, 0 }, 259 { "v8a", "v8", v8, 32, 1, HWS_V8, 0 }, 260 { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, 261 { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 }, 262 { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 }, 263 { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 }, 264 { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 }, 265 { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, 266 { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, 267 268 { "sparc4", "v9b", v9, 0, 1, HWS_VV, 0 }, 269 { "sparc5", "v9b", v9, 0, 1, HWS_VM, HWS2_VM }, 270 271 { "leon", "leon", leon, 32, 1, HWS_V8, 0 }, 272 { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 }, 273 { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 }, 274 { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 }, 275 276 { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, 277 { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 }, 278 { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 }, 279 { "v8plusc", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 }, 280 { "v8plusd", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 }, 281 { "v8pluse", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 }, 282 { "v8plusv", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 }, 283 { "v8plusm", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 }, 284 285 { "v9", "v9", v9, 0, 1, HWS_V9, 0 }, 286 { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 }, 287 { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 }, 288 { "v9c", "v9b", v9, 0, 1, HWS_VC, 0 }, 289 { "v9d", "v9b", v9, 0, 1, HWS_VD, 0 }, 290 { "v9e", "v9b", v9, 0, 1, HWS_VE, 0 }, 291 { "v9v", "v9b", v9, 0, 1, HWS_VV, 0 }, 292 { "v9m", "v9b", v9, 0, 1, HWS_VM, HWS2_VM }, 293 294 /* This exists to allow configure.tgt to pass one 295 value to specify both the default machine and default word size. */ 296 { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 }, 297 { NULL, NULL, v8, 0, 0, 0, 0 } 298 }; 299 300 /* Variant of default_arch */ 301 static enum sparc_arch_types default_arch_type; 302 303 static struct sparc_arch * 304 lookup_arch (char *name) 305 { 306 struct sparc_arch *sa; 307 308 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 309 if (strcmp (sa->name, name) == 0) 310 break; 311 if (sa->name == NULL) 312 return NULL; 313 return sa; 314 } 315 316 /* Initialize the default opcode arch and word size from the default 317 architecture name. */ 318 319 static void 320 init_default_arch (void) 321 { 322 struct sparc_arch *sa = lookup_arch (default_arch); 323 324 if (sa == NULL 325 || sa->default_arch_size == 0) 326 as_fatal (_("Invalid default architecture, broken assembler.")); 327 328 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 329 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 330 as_fatal (_("Bad opcode table, broken assembler.")); 331 default_arch_size = sparc_arch_size = sa->default_arch_size; 332 default_init_p = 1; 333 default_arch_type = sa->arch_type; 334 } 335 336 /* Called by TARGET_FORMAT. */ 337 338 const char * 339 sparc_target_format (void) 340 { 341 /* We don't get a chance to initialize anything before we're called, 342 so handle that now. */ 343 if (! default_init_p) 344 init_default_arch (); 345 346 #ifdef OBJ_AOUT 347 #ifdef TE_NetBSD 348 return "a.out-sparc-netbsd"; 349 #else 350 #ifdef TE_SPARCAOUT 351 if (target_big_endian) 352 return "a.out-sunos-big"; 353 else if (default_arch_type == sparc86x && target_little_endian_data) 354 return "a.out-sunos-big"; 355 else 356 return "a.out-sparc-little"; 357 #else 358 return "a.out-sunos-big"; 359 #endif 360 #endif 361 #endif 362 363 #ifdef OBJ_BOUT 364 return "b.out.big"; 365 #endif 366 367 #ifdef OBJ_COFF 368 #ifdef TE_LYNX 369 return "coff-sparc-lynx"; 370 #else 371 return "coff-sparc"; 372 #endif 373 #endif 374 375 #ifdef TE_VXWORKS 376 return "elf32-sparc-vxworks"; 377 #endif 378 379 #ifdef OBJ_ELF 380 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; 381 #endif 382 383 abort (); 384 } 385 386 /* md_parse_option 388 * Invocation line includes a switch not recognized by the base assembler. 389 * See if it's a processor-specific option. These are: 390 * 391 * -bump 392 * Warn on architecture bumps. See also -A. 393 * 394 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet 395 * Standard 32 bit architectures. 396 * -Av9, -Av9a, -Av9b 397 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 398 * This used to only mean 64 bits, but properly specifying it 399 * complicated gcc's ASM_SPECs, so now opcode selection is 400 * specified orthogonally to word size (except when specifying 401 * the default, but that is an internal implementation detail). 402 * -Av8plus, -Av8plusa, -Av8plusb 403 * Same as -Av9{,a,b}. 404 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 405 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 406 * assembler. 407 * -xarch=v9, -xarch=v9a, -xarch=v9b 408 * Same as -Av9{,a,b} -64, for compatibility with Sun's 409 * assembler. 410 * 411 * Select the architecture and possibly the file format. 412 * Instructions or features not supported by the selected 413 * architecture cause fatal errors. 414 * 415 * The default is to start at v6, and bump the architecture up 416 * whenever an instruction is seen at a higher level. In 32 bit 417 * environments, v9 is not bumped up to, the user must pass 418 * -Av8plus{,a,b}. 419 * 420 * If -bump is specified, a warning is printing when bumping to 421 * higher levels. 422 * 423 * If an architecture is specified, all instructions must match 424 * that architecture. Any higher level instructions are flagged 425 * as errors. Note that in the 32 bit environment specifying 426 * -Av8plus does not automatically create a v8plus object file, a 427 * v9 insn must be seen. 428 * 429 * If both an architecture and -bump are specified, the 430 * architecture starts at the specified level, but bumps are 431 * warnings. Note that we can't set `current_architecture' to 432 * the requested level in this case: in the 32 bit environment, 433 * we still must avoid creating v8plus object files unless v9 434 * insns are seen. 435 * 436 * Note: 437 * Bumping between incompatible architectures is always an 438 * error. For example, from sparclite to v9. 439 */ 440 441 #ifdef OBJ_ELF 442 const char *md_shortopts = "A:K:VQ:sq"; 443 #else 444 #ifdef OBJ_AOUT 445 const char *md_shortopts = "A:k"; 446 #else 447 const char *md_shortopts = "A:"; 448 #endif 449 #endif 450 struct option md_longopts[] = { 451 #define OPTION_BUMP (OPTION_MD_BASE) 452 {"bump", no_argument, NULL, OPTION_BUMP}, 453 #define OPTION_SPARC (OPTION_MD_BASE + 1) 454 {"sparc", no_argument, NULL, OPTION_SPARC}, 455 #define OPTION_XARCH (OPTION_MD_BASE + 2) 456 {"xarch", required_argument, NULL, OPTION_XARCH}, 457 #ifdef OBJ_ELF 458 #define OPTION_32 (OPTION_MD_BASE + 3) 459 {"32", no_argument, NULL, OPTION_32}, 460 #define OPTION_64 (OPTION_MD_BASE + 4) 461 {"64", no_argument, NULL, OPTION_64}, 462 #define OPTION_TSO (OPTION_MD_BASE + 5) 463 {"TSO", no_argument, NULL, OPTION_TSO}, 464 #define OPTION_PSO (OPTION_MD_BASE + 6) 465 {"PSO", no_argument, NULL, OPTION_PSO}, 466 #define OPTION_RMO (OPTION_MD_BASE + 7) 467 {"RMO", no_argument, NULL, OPTION_RMO}, 468 #endif 469 #ifdef SPARC_BIENDIAN 470 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 471 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 472 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 473 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 474 #endif 475 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 476 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 477 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 478 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 479 #ifdef OBJ_ELF 480 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 481 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 482 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 483 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 484 #endif 485 #define OPTION_RELAX (OPTION_MD_BASE + 14) 486 {"relax", no_argument, NULL, OPTION_RELAX}, 487 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 488 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 489 {NULL, no_argument, NULL, 0} 490 }; 491 492 size_t md_longopts_size = sizeof (md_longopts); 493 494 int 495 md_parse_option (int c, char *arg) 496 { 497 /* We don't get a chance to initialize anything before we're called, 498 so handle that now. */ 499 if (! default_init_p) 500 init_default_arch (); 501 502 switch (c) 503 { 504 case OPTION_BUMP: 505 warn_on_bump = 1; 506 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 507 break; 508 509 case OPTION_XARCH: 510 #ifdef OBJ_ELF 511 if (!strncmp (arg, "v9", 2)) 512 md_parse_option (OPTION_64, NULL); 513 else 514 { 515 if (!strncmp (arg, "v8", 2) 516 || !strncmp (arg, "v7", 2) 517 || !strncmp (arg, "v6", 2) 518 || !strcmp (arg, "sparclet") 519 || !strcmp (arg, "sparclite") 520 || !strcmp (arg, "sparc86x")) 521 md_parse_option (OPTION_32, NULL); 522 } 523 #endif 524 /* Fall through. */ 525 526 case 'A': 527 { 528 struct sparc_arch *sa; 529 enum sparc_opcode_arch_val opcode_arch; 530 531 sa = lookup_arch (arg); 532 if (sa == NULL 533 || ! sa->user_option_p) 534 { 535 if (c == OPTION_XARCH) 536 as_bad (_("invalid architecture -xarch=%s"), arg); 537 else 538 as_bad (_("invalid architecture -A%s"), arg); 539 return 0; 540 } 541 542 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 543 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 544 as_fatal (_("Bad opcode table, broken assembler.")); 545 546 if (!architecture_requested 547 || opcode_arch > max_architecture) 548 max_architecture = opcode_arch; 549 hwcap_allowed 550 |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed; 551 architecture_requested = 1; 552 } 553 break; 554 555 case OPTION_SPARC: 556 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 557 break; 558 559 case OPTION_ENFORCE_ALIGNED_DATA: 560 enforce_aligned_data = 1; 561 break; 562 563 #ifdef SPARC_BIENDIAN 564 case OPTION_LITTLE_ENDIAN: 565 target_big_endian = 0; 566 if (default_arch_type != sparclet) 567 as_fatal ("This target does not support -EL"); 568 break; 569 case OPTION_LITTLE_ENDIAN_DATA: 570 target_little_endian_data = 1; 571 target_big_endian = 0; 572 if (default_arch_type != sparc86x 573 && default_arch_type != v9) 574 as_fatal ("This target does not support --little-endian-data"); 575 break; 576 case OPTION_BIG_ENDIAN: 577 target_big_endian = 1; 578 break; 579 #endif 580 581 #ifdef OBJ_AOUT 582 case 'k': 583 sparc_pic_code = 1; 584 break; 585 #endif 586 587 #ifdef OBJ_ELF 588 case OPTION_32: 589 case OPTION_64: 590 { 591 const char **list, **l; 592 593 sparc_arch_size = c == OPTION_32 ? 32 : 64; 594 list = bfd_target_list (); 595 for (l = list; *l != NULL; l++) 596 { 597 if (sparc_arch_size == 32) 598 { 599 if (CONST_STRNEQ (*l, "elf32-sparc")) 600 break; 601 } 602 else 603 { 604 if (CONST_STRNEQ (*l, "elf64-sparc")) 605 break; 606 } 607 } 608 if (*l == NULL) 609 as_fatal (_("No compiled in support for %d bit object file format"), 610 sparc_arch_size); 611 free (list); 612 613 if (sparc_arch_size == 64 614 && max_architecture < SPARC_OPCODE_ARCH_V9) 615 max_architecture = SPARC_OPCODE_ARCH_V9; 616 } 617 break; 618 619 case OPTION_TSO: 620 sparc_memory_model = MM_TSO; 621 break; 622 623 case OPTION_PSO: 624 sparc_memory_model = MM_PSO; 625 break; 626 627 case OPTION_RMO: 628 sparc_memory_model = MM_RMO; 629 break; 630 631 case 'V': 632 print_version_id (); 633 break; 634 635 case 'Q': 636 /* Qy - do emit .comment 637 Qn - do not emit .comment. */ 638 break; 639 640 case 's': 641 /* Use .stab instead of .stab.excl. */ 642 break; 643 644 case 'q': 645 /* quick -- Native assembler does fewer checks. */ 646 break; 647 648 case 'K': 649 if (strcmp (arg, "PIC") != 0) 650 as_warn (_("Unrecognized option following -K")); 651 else 652 sparc_pic_code = 1; 653 break; 654 655 case OPTION_NO_UNDECLARED_REGS: 656 no_undeclared_regs = 1; 657 break; 658 659 case OPTION_UNDECLARED_REGS: 660 no_undeclared_regs = 0; 661 break; 662 #endif 663 664 case OPTION_RELAX: 665 sparc_relax = 1; 666 break; 667 668 case OPTION_NO_RELAX: 669 sparc_relax = 0; 670 break; 671 672 default: 673 return 0; 674 } 675 676 return 1; 677 } 678 679 void 680 md_show_usage (FILE *stream) 681 { 682 const struct sparc_arch *arch; 683 int column; 684 685 /* We don't get a chance to initialize anything before we're called, 686 so handle that now. */ 687 if (! default_init_p) 688 init_default_arch (); 689 690 fprintf (stream, _("SPARC options:\n")); 691 column = 0; 692 for (arch = &sparc_arch_table[0]; arch->name; arch++) 693 { 694 if (!arch->user_option_p) 695 continue; 696 if (arch != &sparc_arch_table[0]) 697 fprintf (stream, " | "); 698 if (column + strlen (arch->name) > 70) 699 { 700 column = 0; 701 fputc ('\n', stream); 702 } 703 column += 5 + 2 + strlen (arch->name); 704 fprintf (stream, "-A%s", arch->name); 705 } 706 for (arch = &sparc_arch_table[0]; arch->name; arch++) 707 { 708 if (!arch->user_option_p) 709 continue; 710 fprintf (stream, " | "); 711 if (column + strlen (arch->name) > 65) 712 { 713 column = 0; 714 fputc ('\n', stream); 715 } 716 column += 5 + 7 + strlen (arch->name); 717 fprintf (stream, "-xarch=%s", arch->name); 718 } 719 fprintf (stream, _("\n\ 720 specify variant of SPARC architecture\n\ 721 -bump warn when assembler switches architectures\n\ 722 -sparc ignored\n\ 723 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 724 -relax relax jumps and branches (default)\n\ 725 -no-relax avoid changing any jumps and branches\n")); 726 #ifdef OBJ_AOUT 727 fprintf (stream, _("\ 728 -k generate PIC\n")); 729 #endif 730 #ifdef OBJ_ELF 731 fprintf (stream, _("\ 732 -32 create 32 bit object file\n\ 733 -64 create 64 bit object file\n")); 734 fprintf (stream, _("\ 735 [default is %d]\n"), default_arch_size); 736 fprintf (stream, _("\ 737 -TSO use Total Store Ordering\n\ 738 -PSO use Partial Store Ordering\n\ 739 -RMO use Relaxed Memory Ordering\n")); 740 fprintf (stream, _("\ 741 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 742 fprintf (stream, _("\ 743 -KPIC generate PIC\n\ 744 -V print assembler version number\n\ 745 -undeclared-regs ignore application global register usage without\n\ 746 appropriate .register directive (default)\n\ 747 -no-undeclared-regs force error on application global register usage\n\ 748 without appropriate .register directive\n\ 749 -q ignored\n\ 750 -Qy, -Qn ignored\n\ 751 -s ignored\n")); 752 #endif 753 #ifdef SPARC_BIENDIAN 754 fprintf (stream, _("\ 755 -EL generate code for a little endian machine\n\ 756 -EB generate code for a big endian machine\n\ 757 --little-endian-data generate code for a machine having big endian\n\ 758 instructions and little endian data.\n")); 759 #endif 760 } 761 762 /* Native operand size opcode translation. */ 764 struct 765 { 766 char *name; 767 char *name32; 768 char *name64; 769 } native_op_table[] = 770 { 771 {"ldn", "ld", "ldx"}, 772 {"ldna", "lda", "ldxa"}, 773 {"stn", "st", "stx"}, 774 {"stna", "sta", "stxa"}, 775 {"slln", "sll", "sllx"}, 776 {"srln", "srl", "srlx"}, 777 {"sran", "sra", "srax"}, 778 {"casn", "cas", "casx"}, 779 {"casna", "casa", "casxa"}, 780 {"clrn", "clr", "clrx"}, 781 {NULL, NULL, NULL}, 782 }; 783 784 /* sparc64 privileged and hyperprivileged registers. */ 786 787 struct priv_reg_entry 788 { 789 char *name; 790 int regnum; 791 }; 792 793 struct priv_reg_entry priv_reg_table[] = 794 { 795 {"tpc", 0}, 796 {"tnpc", 1}, 797 {"tstate", 2}, 798 {"tt", 3}, 799 {"tick", 4}, 800 {"tba", 5}, 801 {"pstate", 6}, 802 {"tl", 7}, 803 {"pil", 8}, 804 {"cwp", 9}, 805 {"cansave", 10}, 806 {"canrestore", 11}, 807 {"cleanwin", 12}, 808 {"otherwin", 13}, 809 {"wstate", 14}, 810 {"fq", 15}, 811 {"gl", 16}, 812 {"ver", 31}, 813 {"", -1}, /* End marker. */ 814 }; 815 816 struct priv_reg_entry hpriv_reg_table[] = 817 { 818 {"hpstate", 0}, 819 {"htstate", 1}, 820 {"hintp", 3}, 821 {"htba", 5}, 822 {"hver", 6}, 823 {"hstick_offset", 28}, 824 {"hstick_enable", 29}, 825 {"hstick_cmpr", 31}, 826 {"", -1}, /* End marker. */ 827 }; 828 829 /* v9a specific asrs. This table is ordered by initial 830 letter, in reverse. */ 831 832 struct priv_reg_entry v9a_asr_table[] = 833 { 834 {"tick_cmpr", 23}, 835 {"sys_tick_cmpr", 25}, 836 {"sys_tick", 24}, 837 {"stick_cmpr", 25}, 838 {"stick", 24}, 839 {"softint_clear", 21}, 840 {"softint_set", 20}, 841 {"softint", 22}, 842 {"set_softint", 20}, 843 {"pause", 27}, 844 {"pic", 17}, 845 {"pcr", 16}, 846 {"mwait", 28}, 847 {"gsr", 19}, 848 {"dcr", 18}, 849 {"cfr", 26}, 850 {"clear_softint", 21}, 851 {"", -1}, /* End marker. */ 852 }; 853 854 static int 855 cmp_reg_entry (const void *parg, const void *qarg) 856 { 857 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 858 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 859 860 return strcmp (q->name, p->name); 861 } 862 863 /* This function is called once, at assembler startup time. It should 865 set up all the tables, etc. that the MD part of the assembler will 866 need. */ 867 868 void 869 md_begin (void) 870 { 871 const char *retval = NULL; 872 int lose = 0; 873 unsigned int i = 0; 874 875 /* We don't get a chance to initialize anything before md_parse_option 876 is called, and it may not be called, so handle default initialization 877 now if not already done. */ 878 if (! default_init_p) 879 init_default_arch (); 880 881 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 882 op_hash = hash_new (); 883 884 while (i < (unsigned int) sparc_num_opcodes) 885 { 886 const char *name = sparc_opcodes[i].name; 887 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); 888 if (retval != NULL) 889 { 890 as_bad (_("Internal error: can't hash `%s': %s\n"), 891 sparc_opcodes[i].name, retval); 892 lose = 1; 893 } 894 do 895 { 896 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 897 { 898 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 899 sparc_opcodes[i].name, sparc_opcodes[i].args); 900 lose = 1; 901 } 902 ++i; 903 } 904 while (i < (unsigned int) sparc_num_opcodes 905 && !strcmp (sparc_opcodes[i].name, name)); 906 } 907 908 for (i = 0; native_op_table[i].name; i++) 909 { 910 const struct sparc_opcode *insn; 911 char *name = ((sparc_arch_size == 32) 912 ? native_op_table[i].name32 913 : native_op_table[i].name64); 914 insn = (struct sparc_opcode *) hash_find (op_hash, name); 915 if (insn == NULL) 916 { 917 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 918 name, native_op_table[i].name); 919 lose = 1; 920 } 921 else 922 { 923 retval = hash_insert (op_hash, native_op_table[i].name, 924 (void *) insn); 925 if (retval != NULL) 926 { 927 as_bad (_("Internal error: can't hash `%s': %s\n"), 928 sparc_opcodes[i].name, retval); 929 lose = 1; 930 } 931 } 932 } 933 934 if (lose) 935 as_fatal (_("Broken assembler. No assembly attempted.")); 936 937 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 938 sizeof (priv_reg_table[0]), cmp_reg_entry); 939 940 /* If -bump, record the architecture level at which we start issuing 941 warnings. The behaviour is different depending upon whether an 942 architecture was explicitly specified. If it wasn't, we issue warnings 943 for all upwards bumps. If it was, we don't start issuing warnings until 944 we need to bump beyond the requested architecture or when we bump between 945 conflicting architectures. */ 946 947 if (warn_on_bump 948 && architecture_requested) 949 { 950 /* `max_architecture' records the requested architecture. 951 Issue warnings if we go above it. */ 952 warn_after_architecture = max_architecture; 953 } 954 955 /* Find the highest architecture level that doesn't conflict with 956 the requested one. */ 957 958 if (warn_on_bump 959 || !architecture_requested) 960 { 961 enum sparc_opcode_arch_val current_max_architecture 962 = max_architecture; 963 964 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 965 max_architecture > warn_after_architecture; 966 --max_architecture) 967 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 968 current_max_architecture)) 969 break; 970 } 971 } 972 973 /* Called after all assembly has been done. */ 974 975 void 976 sparc_md_end (void) 977 { 978 unsigned long mach = bfd_mach_sparc; 979 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 980 int hwcaps, hwcaps2; 981 #endif 982 983 if (sparc_arch_size == 64) 984 switch (current_architecture) 985 { 986 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 987 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 988 default: mach = bfd_mach_sparc_v9; break; 989 } 990 else 991 switch (current_architecture) 992 { 993 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 994 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 995 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 996 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 997 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 998 be but for now it is (since that's the way it's always been 999 treated). */ 1000 default: break; 1001 } 1002 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 1003 1004 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 1005 hwcaps = hwcap_seen & U0xffffffff; 1006 hwcaps2 = hwcap_seen >> 32; 1007 1008 if (hwcaps) 1009 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); 1010 if (hwcaps2) 1011 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); 1012 #endif 1013 } 1014 1015 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 1017 1018 static inline int 1019 in_signed_range (bfd_signed_vma val, bfd_signed_vma max) 1020 { 1021 if (max <= 0) 1022 abort (); 1023 /* Sign-extend the value from the architecture word size, so that 1024 0xffffffff is always considered -1 on sparc32. */ 1025 if (sparc_arch_size == 32) 1026 { 1027 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 1028 val = ((val & U0xffffffff) ^ sign) - sign; 1029 } 1030 if (val > max) 1031 return 0; 1032 if (val < ~max) 1033 return 0; 1034 return 1; 1035 } 1036 1037 /* Return non-zero if VAL is in the range 0 to MAX. */ 1038 1039 static inline int 1040 in_unsigned_range (bfd_vma val, bfd_vma max) 1041 { 1042 if (val > max) 1043 return 0; 1044 return 1; 1045 } 1046 1047 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 1048 (e.g. -15 to +31). */ 1049 1050 static inline int 1051 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) 1052 { 1053 if (max <= 0) 1054 abort (); 1055 if (val > max) 1056 return 0; 1057 if (val < ~(max >> 1)) 1058 return 0; 1059 return 1; 1060 } 1061 1062 static int 1063 sparc_ffs (unsigned int mask) 1064 { 1065 int i; 1066 1067 if (mask == 0) 1068 return -1; 1069 1070 for (i = 0; (mask & 1) == 0; ++i) 1071 mask >>= 1; 1072 return i; 1073 } 1074 1075 /* Implement big shift right. */ 1076 static bfd_vma 1077 BSR (bfd_vma val, int amount) 1078 { 1079 if (sizeof (bfd_vma) <= 4 && amount >= 32) 1080 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 1081 return val >> amount; 1082 } 1083 1084 /* For communication between sparc_ip and get_expression. */ 1086 static char *expr_end; 1087 1088 /* Values for `special_case'. 1089 Instructions that require wierd handling because they're longer than 1090 4 bytes. */ 1091 #define SPECIAL_CASE_NONE 0 1092 #define SPECIAL_CASE_SET 1 1093 #define SPECIAL_CASE_SETSW 2 1094 #define SPECIAL_CASE_SETX 3 1095 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1096 #define SPECIAL_CASE_FDIV 4 1097 1098 /* Bit masks of various insns. */ 1099 #define NOP_INSN 0x01000000 1100 #define OR_INSN 0x80100000 1101 #define XOR_INSN 0x80180000 1102 #define FMOVS_INSN 0x81A00020 1103 #define SETHI_INSN 0x01000000 1104 #define SLLX_INSN 0x81281000 1105 #define SRA_INSN 0x81380000 1106 1107 /* The last instruction to be assembled. */ 1108 static const struct sparc_opcode *last_insn; 1109 /* The assembled opcode of `last_insn'. */ 1110 static unsigned long last_opcode; 1111 1112 /* Handle the set and setuw synthetic instructions. */ 1114 1115 static void 1116 synthetize_setuw (const struct sparc_opcode *insn) 1117 { 1118 int need_hi22_p = 0; 1119 int rd = (the_insn.opcode & RD (~0)) >> 25; 1120 1121 if (the_insn.exp.X_op == O_constant) 1122 { 1123 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1124 { 1125 if (sizeof (offsetT) > 4 1126 && (the_insn.exp.X_add_number < 0 1127 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1128 as_warn (_("set: number not in 0..4294967295 range")); 1129 } 1130 else 1131 { 1132 if (sizeof (offsetT) > 4 1133 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1134 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1135 as_warn (_("set: number not in -2147483648..4294967295 range")); 1136 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1137 } 1138 } 1139 1140 /* See if operand is absolute and small; skip sethi if so. */ 1141 if (the_insn.exp.X_op != O_constant 1142 || the_insn.exp.X_add_number >= (1 << 12) 1143 || the_insn.exp.X_add_number < -(1 << 12)) 1144 { 1145 the_insn.opcode = (SETHI_INSN | RD (rd) 1146 | ((the_insn.exp.X_add_number >> 10) 1147 & (the_insn.exp.X_op == O_constant 1148 ? 0x3fffff : 0))); 1149 the_insn.reloc = (the_insn.exp.X_op != O_constant 1150 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1151 output_insn (insn, &the_insn); 1152 need_hi22_p = 1; 1153 } 1154 1155 /* See if operand has no low-order bits; skip OR if so. */ 1156 if (the_insn.exp.X_op != O_constant 1157 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1158 || ! need_hi22_p) 1159 { 1160 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1161 | RD (rd) | IMMED 1162 | (the_insn.exp.X_add_number 1163 & (the_insn.exp.X_op != O_constant 1164 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1165 the_insn.reloc = (the_insn.exp.X_op != O_constant 1166 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1167 output_insn (insn, &the_insn); 1168 } 1169 } 1170 1171 /* Handle the setsw synthetic instruction. */ 1172 1173 static void 1174 synthetize_setsw (const struct sparc_opcode *insn) 1175 { 1176 int low32, rd, opc; 1177 1178 rd = (the_insn.opcode & RD (~0)) >> 25; 1179 1180 if (the_insn.exp.X_op != O_constant) 1181 { 1182 synthetize_setuw (insn); 1183 1184 /* Need to sign extend it. */ 1185 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1186 the_insn.reloc = BFD_RELOC_NONE; 1187 output_insn (insn, &the_insn); 1188 return; 1189 } 1190 1191 if (sizeof (offsetT) > 4 1192 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1193 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1194 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1195 1196 low32 = the_insn.exp.X_add_number; 1197 1198 if (low32 >= 0) 1199 { 1200 synthetize_setuw (insn); 1201 return; 1202 } 1203 1204 opc = OR_INSN; 1205 1206 the_insn.reloc = BFD_RELOC_NONE; 1207 /* See if operand is absolute and small; skip sethi if so. */ 1208 if (low32 < -(1 << 12)) 1209 { 1210 the_insn.opcode = (SETHI_INSN | RD (rd) 1211 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1212 output_insn (insn, &the_insn); 1213 low32 = 0x1c00 | (low32 & 0x3ff); 1214 opc = RS1 (rd) | XOR_INSN; 1215 } 1216 1217 the_insn.opcode = (opc | RD (rd) | IMMED 1218 | (low32 & 0x1fff)); 1219 output_insn (insn, &the_insn); 1220 } 1221 1222 /* Handle the setsw synthetic instruction. */ 1223 1224 static void 1225 synthetize_setx (const struct sparc_opcode *insn) 1226 { 1227 int upper32, lower32; 1228 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1229 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1230 int upper_dstreg; 1231 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1232 int need_xor10_p = 0; 1233 1234 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1235 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1236 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1237 #undef SIGNEXT32 1238 1239 upper_dstreg = tmpreg; 1240 /* The tmp reg should not be the dst reg. */ 1241 if (tmpreg == dstreg) 1242 as_warn (_("setx: temporary register same as destination register")); 1243 1244 /* ??? Obviously there are other optimizations we can do 1245 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1246 doing some of these. Later. If you do change things, try to 1247 change all of this to be table driven as well. */ 1248 /* What to output depends on the number if it's constant. 1249 Compute that first, then output what we've decided upon. */ 1250 if (the_insn.exp.X_op != O_constant) 1251 { 1252 if (sparc_arch_size == 32) 1253 { 1254 /* When arch size is 32, we want setx to be equivalent 1255 to setuw for anything but constants. */ 1256 the_insn.exp.X_add_number &= 0xffffffff; 1257 synthetize_setuw (insn); 1258 return; 1259 } 1260 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1261 lower32 = 0; 1262 upper32 = 0; 1263 } 1264 else 1265 { 1266 /* Reset X_add_number, we've extracted it as upper32/lower32. 1267 Otherwise fixup_segment will complain about not being able to 1268 write an 8 byte number in a 4 byte field. */ 1269 the_insn.exp.X_add_number = 0; 1270 1271 /* Only need hh22 if `or' insn can't handle constant. */ 1272 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1273 need_hh22_p = 1; 1274 1275 /* Does bottom part (after sethi) have bits? */ 1276 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1277 /* No hh22, but does upper32 still have bits we can't set 1278 from lower32? */ 1279 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1280 need_hm10_p = 1; 1281 1282 /* If the lower half is all zero, we build the upper half directly 1283 into the dst reg. */ 1284 if (lower32 != 0 1285 /* Need lower half if number is zero or 0xffffffff00000000. */ 1286 || (! need_hh22_p && ! need_hm10_p)) 1287 { 1288 /* No need for sethi if `or' insn can handle constant. */ 1289 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1290 /* Note that we can't use a negative constant in the `or' 1291 insn unless the upper 32 bits are all ones. */ 1292 || (lower32 < 0 && upper32 != -1) 1293 || (lower32 >= 0 && upper32 == -1)) 1294 need_hi22_p = 1; 1295 1296 if (need_hi22_p && upper32 == -1) 1297 need_xor10_p = 1; 1298 1299 /* Does bottom part (after sethi) have bits? */ 1300 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1301 /* No sethi. */ 1302 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1303 /* Need `or' if we didn't set anything else. */ 1304 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1305 need_lo10_p = 1; 1306 } 1307 else 1308 /* Output directly to dst reg if lower 32 bits are all zero. */ 1309 upper_dstreg = dstreg; 1310 } 1311 1312 if (!upper_dstreg && dstreg) 1313 as_warn (_("setx: illegal temporary register g0")); 1314 1315 if (need_hh22_p) 1316 { 1317 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1318 | ((upper32 >> 10) & 0x3fffff)); 1319 the_insn.reloc = (the_insn.exp.X_op != O_constant 1320 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1321 output_insn (insn, &the_insn); 1322 } 1323 1324 if (need_hi22_p) 1325 { 1326 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1327 | (((need_xor10_p ? ~lower32 : lower32) 1328 >> 10) & 0x3fffff)); 1329 the_insn.reloc = (the_insn.exp.X_op != O_constant 1330 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1331 output_insn (insn, &the_insn); 1332 } 1333 1334 if (need_hm10_p) 1335 { 1336 the_insn.opcode = (OR_INSN 1337 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1338 | RD (upper_dstreg) 1339 | IMMED 1340 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1341 the_insn.reloc = (the_insn.exp.X_op != O_constant 1342 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1343 output_insn (insn, &the_insn); 1344 } 1345 1346 if (need_lo10_p) 1347 { 1348 /* FIXME: One nice optimization to do here is to OR the low part 1349 with the highpart if hi22 isn't needed and the low part is 1350 positive. */ 1351 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1352 | RD (dstreg) 1353 | IMMED 1354 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1355 the_insn.reloc = (the_insn.exp.X_op != O_constant 1356 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1357 output_insn (insn, &the_insn); 1358 } 1359 1360 /* If we needed to build the upper part, shift it into place. */ 1361 if (need_hh22_p || need_hm10_p) 1362 { 1363 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1364 | IMMED | 32); 1365 the_insn.reloc = BFD_RELOC_NONE; 1366 output_insn (insn, &the_insn); 1367 } 1368 1369 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1370 if (need_xor10_p) 1371 { 1372 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1373 | 0x1c00 | (lower32 & 0x3ff)); 1374 the_insn.reloc = BFD_RELOC_NONE; 1375 output_insn (insn, &the_insn); 1376 } 1377 1378 /* If we needed to build both upper and lower parts, OR them together. */ 1379 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1380 { 1381 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1382 | RD (dstreg)); 1383 the_insn.reloc = BFD_RELOC_NONE; 1384 output_insn (insn, &the_insn); 1385 } 1386 } 1387 1388 /* Main entry point to assemble one instruction. */ 1390 1391 void 1392 md_assemble (char *str) 1393 { 1394 const struct sparc_opcode *insn; 1395 int special_case; 1396 1397 know (str); 1398 special_case = sparc_ip (str, &insn); 1399 if (insn == NULL) 1400 return; 1401 1402 /* We warn about attempts to put a floating point branch in a delay slot, 1403 unless the delay slot has been annulled. */ 1404 if (last_insn != NULL 1405 && (insn->flags & F_FBR) != 0 1406 && (last_insn->flags & F_DELAYED) != 0 1407 /* ??? This test isn't completely accurate. We assume anything with 1408 F_{UNBR,CONDBR,FBR} set is annullable. */ 1409 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1410 || (last_opcode & ANNUL) == 0)) 1411 as_warn (_("FP branch in delay slot")); 1412 1413 /* SPARC before v9 requires a nop instruction between a floating 1414 point instruction and a floating point branch. We insert one 1415 automatically, with a warning. */ 1416 if (max_architecture < SPARC_OPCODE_ARCH_V9 1417 && last_insn != NULL 1418 && (insn->flags & F_FBR) != 0 1419 && (last_insn->flags & F_FLOAT) != 0) 1420 { 1421 struct sparc_it nop_insn; 1422 1423 nop_insn.opcode = NOP_INSN; 1424 nop_insn.reloc = BFD_RELOC_NONE; 1425 output_insn (insn, &nop_insn); 1426 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1427 } 1428 1429 switch (special_case) 1430 { 1431 case SPECIAL_CASE_NONE: 1432 /* Normal insn. */ 1433 output_insn (insn, &the_insn); 1434 break; 1435 1436 case SPECIAL_CASE_SETSW: 1437 synthetize_setsw (insn); 1438 break; 1439 1440 case SPECIAL_CASE_SET: 1441 synthetize_setuw (insn); 1442 break; 1443 1444 case SPECIAL_CASE_SETX: 1445 synthetize_setx (insn); 1446 break; 1447 1448 case SPECIAL_CASE_FDIV: 1449 { 1450 int rd = (the_insn.opcode >> 25) & 0x1f; 1451 1452 output_insn (insn, &the_insn); 1453 1454 /* According to information leaked from Sun, the "fdiv" instructions 1455 on early SPARC machines would produce incorrect results sometimes. 1456 The workaround is to add an fmovs of the destination register to 1457 itself just after the instruction. This was true on machines 1458 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1459 gas_assert (the_insn.reloc == BFD_RELOC_NONE); 1460 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1461 output_insn (insn, &the_insn); 1462 return; 1463 } 1464 1465 default: 1466 as_fatal (_("failed special case insn sanity check")); 1467 } 1468 } 1469 1470 static const char * 1471 get_hwcap_name (bfd_uint64_t mask) 1472 { 1473 if (mask & HWCAP_MUL32) 1474 return "mul32"; 1475 if (mask & HWCAP_DIV32) 1476 return "div32"; 1477 if (mask & HWCAP_FSMULD) 1478 return "fsmuld"; 1479 if (mask & HWCAP_V8PLUS) 1480 return "v8plus"; 1481 if (mask & HWCAP_POPC) 1482 return "popc"; 1483 if (mask & HWCAP_VIS) 1484 return "vis"; 1485 if (mask & HWCAP_VIS2) 1486 return "vis2"; 1487 if (mask & HWCAP_ASI_BLK_INIT) 1488 return "ASIBlkInit"; 1489 if (mask & HWCAP_FMAF) 1490 return "fmaf"; 1491 if (mask & HWCAP_VIS3) 1492 return "vis3"; 1493 if (mask & HWCAP_HPC) 1494 return "hpc"; 1495 if (mask & HWCAP_RANDOM) 1496 return "random"; 1497 if (mask & HWCAP_TRANS) 1498 return "trans"; 1499 if (mask & HWCAP_FJFMAU) 1500 return "fjfmau"; 1501 if (mask & HWCAP_IMA) 1502 return "ima"; 1503 if (mask & HWCAP_ASI_CACHE_SPARING) 1504 return "cspare"; 1505 if (mask & HWCAP_AES) 1506 return "aes"; 1507 if (mask & HWCAP_DES) 1508 return "des"; 1509 if (mask & HWCAP_KASUMI) 1510 return "kasumi"; 1511 if (mask & HWCAP_CAMELLIA) 1512 return "camellia"; 1513 if (mask & HWCAP_MD5) 1514 return "md5"; 1515 if (mask & HWCAP_SHA1) 1516 return "sha1"; 1517 if (mask & HWCAP_SHA256) 1518 return "sha256"; 1519 if (mask & HWCAP_SHA512) 1520 return "sha512"; 1521 if (mask & HWCAP_MPMUL) 1522 return "mpmul"; 1523 if (mask & HWCAP_MONT) 1524 return "mont"; 1525 if (mask & HWCAP_PAUSE) 1526 return "pause"; 1527 if (mask & HWCAP_CBCOND) 1528 return "cbcond"; 1529 if (mask & HWCAP_CRC32C) 1530 return "crc32c"; 1531 1532 mask = mask >> 32; 1533 if (mask & HWCAP2_FJATHPLUS) 1534 return "fjathplus"; 1535 if (mask & HWCAP2_VIS3B) 1536 return "vis3b"; 1537 if (mask & HWCAP2_ADP) 1538 return "adp"; 1539 if (mask & HWCAP2_SPARC5) 1540 return "sparc5"; 1541 if (mask & HWCAP2_MWAIT) 1542 return "mwait"; 1543 if (mask & HWCAP2_XMPMUL) 1544 return "xmpmul"; 1545 if (mask & HWCAP2_XMONT) 1546 return "xmont"; 1547 if (mask & HWCAP2_NSEC) 1548 return "nsec"; 1549 1550 return "UNKNOWN"; 1551 } 1552 1553 /* Subroutine of md_assemble to do the actual parsing. */ 1554 1555 static int 1556 sparc_ip (char *str, const struct sparc_opcode **pinsn) 1557 { 1558 char *error_message = ""; 1559 char *s; 1560 const char *args; 1561 char c; 1562 const struct sparc_opcode *insn; 1563 char *argsStart; 1564 unsigned long opcode; 1565 unsigned int mask = 0; 1566 int match = 0; 1567 int comma = 0; 1568 int v9_arg_p; 1569 int special_case = SPECIAL_CASE_NONE; 1570 1571 s = str; 1572 if (ISLOWER (*s)) 1573 { 1574 do 1575 ++s; 1576 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); 1577 } 1578 1579 switch (*s) 1580 { 1581 case '\0': 1582 break; 1583 1584 case ',': 1585 comma = 1; 1586 /* Fall through. */ 1587 1588 case ' ': 1589 *s++ = '\0'; 1590 break; 1591 1592 default: 1593 as_bad (_("Unknown opcode: `%s'"), str); 1594 *pinsn = NULL; 1595 return special_case; 1596 } 1597 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1598 *pinsn = insn; 1599 if (insn == NULL) 1600 { 1601 as_bad (_("Unknown opcode: `%s'"), str); 1602 return special_case; 1603 } 1604 if (comma) 1605 { 1606 *--s = ','; 1607 } 1608 1609 argsStart = s; 1610 for (;;) 1611 { 1612 opcode = insn->match; 1613 memset (&the_insn, '\0', sizeof (the_insn)); 1614 the_insn.reloc = BFD_RELOC_NONE; 1615 v9_arg_p = 0; 1616 1617 /* Build the opcode, checking as we go to make sure that the 1618 operands match. */ 1619 for (args = insn->args;; ++args) 1620 { 1621 switch (*args) 1622 { 1623 case 'K': 1624 { 1625 int kmask = 0; 1626 1627 /* Parse a series of masks. */ 1628 if (*s == '#') 1629 { 1630 while (*s == '#') 1631 { 1632 int jmask; 1633 1634 if (! parse_keyword_arg (sparc_encode_membar, &s, 1635 &jmask)) 1636 { 1637 error_message = _(": invalid membar mask name"); 1638 goto error; 1639 } 1640 kmask |= jmask; 1641 while (*s == ' ') 1642 ++s; 1643 if (*s == '|' || *s == '+') 1644 ++s; 1645 while (*s == ' ') 1646 ++s; 1647 } 1648 } 1649 else 1650 { 1651 if (! parse_const_expr_arg (&s, &kmask)) 1652 { 1653 error_message = _(": invalid membar mask expression"); 1654 goto error; 1655 } 1656 if (kmask < 0 || kmask > 127) 1657 { 1658 error_message = _(": invalid membar mask number"); 1659 goto error; 1660 } 1661 } 1662 1663 opcode |= MEMBAR (kmask); 1664 continue; 1665 } 1666 1667 case '3': 1668 { 1669 int smask = 0; 1670 1671 if (! parse_const_expr_arg (&s, &smask)) 1672 { 1673 error_message = _(": invalid siam mode expression"); 1674 goto error; 1675 } 1676 if (smask < 0 || smask > 7) 1677 { 1678 error_message = _(": invalid siam mode number"); 1679 goto error; 1680 } 1681 opcode |= smask; 1682 continue; 1683 } 1684 1685 case '*': 1686 { 1687 int fcn = 0; 1688 1689 /* Parse a prefetch function. */ 1690 if (*s == '#') 1691 { 1692 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1693 { 1694 error_message = _(": invalid prefetch function name"); 1695 goto error; 1696 } 1697 } 1698 else 1699 { 1700 if (! parse_const_expr_arg (&s, &fcn)) 1701 { 1702 error_message = _(": invalid prefetch function expression"); 1703 goto error; 1704 } 1705 if (fcn < 0 || fcn > 31) 1706 { 1707 error_message = _(": invalid prefetch function number"); 1708 goto error; 1709 } 1710 } 1711 opcode |= RD (fcn); 1712 continue; 1713 } 1714 1715 case '!': 1716 case '?': 1717 /* Parse a sparc64 privileged register. */ 1718 if (*s == '%') 1719 { 1720 struct priv_reg_entry *p = priv_reg_table; 1721 unsigned int len = 9999999; /* Init to make gcc happy. */ 1722 1723 s += 1; 1724 while (p->name[0] > s[0]) 1725 p++; 1726 while (p->name[0] == s[0]) 1727 { 1728 len = strlen (p->name); 1729 if (strncmp (p->name, s, len) == 0) 1730 break; 1731 p++; 1732 } 1733 if (p->name[0] != s[0]) 1734 { 1735 error_message = _(": unrecognizable privileged register"); 1736 goto error; 1737 } 1738 if (*args == '?') 1739 opcode |= (p->regnum << 14); 1740 else 1741 opcode |= (p->regnum << 25); 1742 s += len; 1743 continue; 1744 } 1745 else 1746 { 1747 error_message = _(": unrecognizable privileged register"); 1748 goto error; 1749 } 1750 1751 case '$': 1752 case '%': 1753 /* Parse a sparc64 hyperprivileged register. */ 1754 if (*s == '%') 1755 { 1756 struct priv_reg_entry *p = hpriv_reg_table; 1757 unsigned int len = 9999999; /* Init to make gcc happy. */ 1758 1759 s += 1; 1760 while (p->name[0] > s[0]) 1761 p++; 1762 while (p->name[0] == s[0]) 1763 { 1764 len = strlen (p->name); 1765 if (strncmp (p->name, s, len) == 0) 1766 break; 1767 p++; 1768 } 1769 if (p->name[0] != s[0]) 1770 { 1771 error_message = _(": unrecognizable hyperprivileged register"); 1772 goto error; 1773 } 1774 if (*args == '$') 1775 opcode |= (p->regnum << 14); 1776 else 1777 opcode |= (p->regnum << 25); 1778 s += len; 1779 continue; 1780 } 1781 else 1782 { 1783 error_message = _(": unrecognizable hyperprivileged register"); 1784 goto error; 1785 } 1786 1787 case '_': 1788 case '/': 1789 /* Parse a v9a/v9b ancillary state register. */ 1790 if (*s == '%') 1791 { 1792 struct priv_reg_entry *p = v9a_asr_table; 1793 unsigned int len = 9999999; /* Init to make gcc happy. */ 1794 1795 s += 1; 1796 while (p->name[0] > s[0]) 1797 p++; 1798 while (p->name[0] == s[0]) 1799 { 1800 len = strlen (p->name); 1801 if (strncmp (p->name, s, len) == 0) 1802 break; 1803 p++; 1804 } 1805 if (p->name[0] != s[0]) 1806 { 1807 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1808 goto error; 1809 } 1810 if (*args == '/' && (p->regnum == 20 || p->regnum == 21)) 1811 { 1812 error_message = _(": rd on write only ancillary state register"); 1813 goto error; 1814 } 1815 if (p->regnum >= 24 1816 && (insn->architecture 1817 & SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A))) 1818 { 1819 /* %sys_tick and %sys_tick_cmpr are v9bnotv9a */ 1820 error_message = _(": unrecognizable v9a ancillary state register"); 1821 goto error; 1822 } 1823 if (*args == '/') 1824 opcode |= (p->regnum << 14); 1825 else 1826 opcode |= (p->regnum << 25); 1827 s += len; 1828 continue; 1829 } 1830 else 1831 { 1832 error_message = _(": unrecognizable v9a or v9b ancillary state register"); 1833 goto error; 1834 } 1835 1836 case 'M': 1837 case 'm': 1838 if (strncmp (s, "%asr", 4) == 0) 1839 { 1840 s += 4; 1841 1842 if (ISDIGIT (*s)) 1843 { 1844 long num = 0; 1845 1846 while (ISDIGIT (*s)) 1847 { 1848 num = num * 10 + *s - '0'; 1849 ++s; 1850 } 1851 1852 if (current_architecture >= SPARC_OPCODE_ARCH_V9) 1853 { 1854 if (num < 16 || 31 < num) 1855 { 1856 error_message = _(": asr number must be between 16 and 31"); 1857 goto error; 1858 } 1859 } 1860 else 1861 { 1862 if (num < 0 || 31 < num) 1863 { 1864 error_message = _(": asr number must be between 0 and 31"); 1865 goto error; 1866 } 1867 } 1868 1869 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 1870 continue; 1871 } 1872 else 1873 { 1874 error_message = _(": expecting %asrN"); 1875 goto error; 1876 } 1877 } /* if %asr */ 1878 break; 1879 1880 case 'I': 1881 the_insn.reloc = BFD_RELOC_SPARC_11; 1882 goto immediate; 1883 1884 case 'j': 1885 the_insn.reloc = BFD_RELOC_SPARC_10; 1886 goto immediate; 1887 1888 case ')': 1889 if (*s == ' ') 1890 s++; 1891 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) 1892 || ISDIGIT (*s)) 1893 { 1894 long num = 0; 1895 1896 if (s[0] == '0' && s[1] == 'x') 1897 { 1898 s += 2; 1899 while (ISXDIGIT (*s)) 1900 { 1901 num <<= 4; 1902 num |= hex_value (*s); 1903 ++s; 1904 } 1905 } 1906 else 1907 { 1908 while (ISDIGIT (*s)) 1909 { 1910 num = num * 10 + *s - '0'; 1911 ++s; 1912 } 1913 } 1914 if (num < 0 || num > 31) 1915 { 1916 error_message = _(": crypto immediate must be between 0 and 31"); 1917 goto error; 1918 } 1919 1920 opcode |= RS3 (num); 1921 continue; 1922 } 1923 else 1924 { 1925 error_message = _(": expecting crypto immediate"); 1926 goto error; 1927 } 1928 1929 case 'X': 1930 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 1931 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1932 the_insn.reloc = BFD_RELOC_SPARC_5; 1933 else 1934 the_insn.reloc = BFD_RELOC_SPARC13; 1935 /* These fields are unsigned, but for upward compatibility, 1936 allow negative values as well. */ 1937 goto immediate; 1938 1939 case 'Y': 1940 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 1941 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1942 the_insn.reloc = BFD_RELOC_SPARC_6; 1943 else 1944 the_insn.reloc = BFD_RELOC_SPARC13; 1945 /* These fields are unsigned, but for upward compatibility, 1946 allow negative values as well. */ 1947 goto immediate; 1948 1949 case 'k': 1950 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 1951 the_insn.pcrel = 1; 1952 goto immediate; 1953 1954 case '=': 1955 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; 1956 the_insn.pcrel = 1; 1957 goto immediate; 1958 1959 case 'G': 1960 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 1961 the_insn.pcrel = 1; 1962 goto immediate; 1963 1964 case 'N': 1965 if (*s == 'p' && s[1] == 'n') 1966 { 1967 s += 2; 1968 continue; 1969 } 1970 break; 1971 1972 case 'T': 1973 if (*s == 'p' && s[1] == 't') 1974 { 1975 s += 2; 1976 continue; 1977 } 1978 break; 1979 1980 case 'z': 1981 if (*s == ' ') 1982 { 1983 ++s; 1984 } 1985 if (strncmp (s, "%icc", 4) == 0) 1986 { 1987 s += 4; 1988 continue; 1989 } 1990 break; 1991 1992 case 'Z': 1993 if (*s == ' ') 1994 { 1995 ++s; 1996 } 1997 if (strncmp (s, "%xcc", 4) == 0) 1998 { 1999 s += 4; 2000 continue; 2001 } 2002 break; 2003 2004 case '6': 2005 if (*s == ' ') 2006 { 2007 ++s; 2008 } 2009 if (strncmp (s, "%fcc0", 5) == 0) 2010 { 2011 s += 5; 2012 continue; 2013 } 2014 break; 2015 2016 case '7': 2017 if (*s == ' ') 2018 { 2019 ++s; 2020 } 2021 if (strncmp (s, "%fcc1", 5) == 0) 2022 { 2023 s += 5; 2024 continue; 2025 } 2026 break; 2027 2028 case '8': 2029 if (*s == ' ') 2030 { 2031 ++s; 2032 } 2033 if (strncmp (s, "%fcc2", 5) == 0) 2034 { 2035 s += 5; 2036 continue; 2037 } 2038 break; 2039 2040 case '9': 2041 if (*s == ' ') 2042 { 2043 ++s; 2044 } 2045 if (strncmp (s, "%fcc3", 5) == 0) 2046 { 2047 s += 5; 2048 continue; 2049 } 2050 break; 2051 2052 case 'P': 2053 if (strncmp (s, "%pc", 3) == 0) 2054 { 2055 s += 3; 2056 continue; 2057 } 2058 break; 2059 2060 case 'W': 2061 if (strncmp (s, "%tick", 5) == 0) 2062 { 2063 s += 5; 2064 continue; 2065 } 2066 break; 2067 2068 case '\0': /* End of args. */ 2069 if (s[0] == ',' && s[1] == '%') 2070 { 2071 static const struct ops 2072 { 2073 /* The name as it appears in assembler. */ 2074 char *name; 2075 /* strlen (name), precomputed for speed */ 2076 int len; 2077 /* The reloc this pseudo-op translates to. */ 2078 int reloc; 2079 /* 1 if tls call. */ 2080 int tls_call; 2081 } 2082 ops[] = 2083 { 2084 { "tgd_add", 7, BFD_RELOC_SPARC_TLS_GD_ADD, 0 }, 2085 { "tgd_call", 8, BFD_RELOC_SPARC_TLS_GD_CALL, 1 }, 2086 { "tldm_add", 8, BFD_RELOC_SPARC_TLS_LDM_ADD, 0 }, 2087 { "tldm_call", 9, BFD_RELOC_SPARC_TLS_LDM_CALL, 1 }, 2088 { "tldo_add", 8, BFD_RELOC_SPARC_TLS_LDO_ADD, 0 }, 2089 { "tie_ldx", 7, BFD_RELOC_SPARC_TLS_IE_LDX, 0 }, 2090 { "tie_ld", 6, BFD_RELOC_SPARC_TLS_IE_LD, 0 }, 2091 { "tie_add", 7, BFD_RELOC_SPARC_TLS_IE_ADD, 0 }, 2092 { "gdop", 4, BFD_RELOC_SPARC_GOTDATA_OP, 0 }, 2093 { NULL, 0, 0, 0 } 2094 }; 2095 const struct ops *o; 2096 char *s1; 2097 int npar = 0; 2098 2099 for (o = ops; o->name; o++) 2100 if (strncmp (s + 2, o->name, o->len) == 0) 2101 break; 2102 if (o->name == NULL) 2103 break; 2104 2105 if (s[o->len + 2] != '(') 2106 { 2107 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2108 return special_case; 2109 } 2110 2111 if (! o->tls_call && the_insn.reloc != BFD_RELOC_NONE) 2112 { 2113 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 2114 o->name); 2115 return special_case; 2116 } 2117 2118 if (o->tls_call 2119 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 2120 || the_insn.exp.X_add_number != 0 2121 || the_insn.exp.X_add_symbol 2122 != symbol_find_or_make ("__tls_get_addr"))) 2123 { 2124 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 2125 o->name); 2126 return special_case; 2127 } 2128 2129 the_insn.reloc = o->reloc; 2130 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2131 s += o->len + 3; 2132 2133 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2134 if (*s1 == '(') 2135 npar++; 2136 else if (*s1 == ')') 2137 { 2138 if (!npar) 2139 break; 2140 npar--; 2141 } 2142 2143 if (*s1 != ')') 2144 { 2145 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2146 return special_case; 2147 } 2148 2149 *s1 = '\0'; 2150 (void) get_expression (s); 2151 *s1 = ')'; 2152 s = s1 + 1; 2153 } 2154 if (*s == '\0') 2155 match = 1; 2156 break; 2157 2158 case '+': 2159 if (*s == '+') 2160 { 2161 ++s; 2162 continue; 2163 } 2164 if (*s == '-') 2165 { 2166 continue; 2167 } 2168 break; 2169 2170 case '[': /* These must match exactly. */ 2171 case ']': 2172 case ',': 2173 case ' ': 2174 if (*s++ == *args) 2175 continue; 2176 break; 2177 2178 case '#': /* Must be at least one digit. */ 2179 if (ISDIGIT (*s++)) 2180 { 2181 while (ISDIGIT (*s)) 2182 { 2183 ++s; 2184 } 2185 continue; 2186 } 2187 break; 2188 2189 case 'C': /* Coprocessor state register. */ 2190 if (strncmp (s, "%csr", 4) == 0) 2191 { 2192 s += 4; 2193 continue; 2194 } 2195 break; 2196 2197 case 'b': /* Next operand is a coprocessor register. */ 2198 case 'c': 2199 case 'D': 2200 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 2201 { 2202 mask = *s++; 2203 if (ISDIGIT (*s)) 2204 { 2205 mask = 10 * (mask - '0') + (*s++ - '0'); 2206 if (mask >= 32) 2207 { 2208 break; 2209 } 2210 } 2211 else 2212 { 2213 mask -= '0'; 2214 } 2215 switch (*args) 2216 { 2217 2218 case 'b': 2219 opcode |= mask << 14; 2220 continue; 2221 2222 case 'c': 2223 opcode |= mask; 2224 continue; 2225 2226 case 'D': 2227 opcode |= mask << 25; 2228 continue; 2229 } 2230 } 2231 break; 2232 2233 case 'r': /* next operand must be a register */ 2234 case 'O': 2235 case '1': 2236 case '2': 2237 case 'd': 2238 if (*s++ == '%') 2239 { 2240 switch (c = *s++) 2241 { 2242 2243 case 'f': /* frame pointer */ 2244 if (*s++ == 'p') 2245 { 2246 mask = 0x1e; 2247 break; 2248 } 2249 goto error; 2250 2251 case 'g': /* global register */ 2252 c = *s++; 2253 if (isoctal (c)) 2254 { 2255 mask = c - '0'; 2256 break; 2257 } 2258 goto error; 2259 2260 case 'i': /* in register */ 2261 c = *s++; 2262 if (isoctal (c)) 2263 { 2264 mask = c - '0' + 24; 2265 break; 2266 } 2267 goto error; 2268 2269 case 'l': /* local register */ 2270 c = *s++; 2271 if (isoctal (c)) 2272 { 2273 mask = (c - '0' + 16); 2274 break; 2275 } 2276 goto error; 2277 2278 case 'o': /* out register */ 2279 c = *s++; 2280 if (isoctal (c)) 2281 { 2282 mask = (c - '0' + 8); 2283 break; 2284 } 2285 goto error; 2286 2287 case 's': /* stack pointer */ 2288 if (*s++ == 'p') 2289 { 2290 mask = 0xe; 2291 break; 2292 } 2293 goto error; 2294 2295 case 'r': /* any register */ 2296 if (!ISDIGIT ((c = *s++))) 2297 { 2298 goto error; 2299 } 2300 /* FALLTHROUGH */ 2301 case '0': 2302 case '1': 2303 case '2': 2304 case '3': 2305 case '4': 2306 case '5': 2307 case '6': 2308 case '7': 2309 case '8': 2310 case '9': 2311 if (ISDIGIT (*s)) 2312 { 2313 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2314 { 2315 goto error; 2316 } 2317 } 2318 else 2319 { 2320 c -= '0'; 2321 } 2322 mask = c; 2323 break; 2324 2325 default: 2326 goto error; 2327 } 2328 2329 if ((mask & ~1) == 2 && sparc_arch_size == 64 2330 && no_undeclared_regs && ! globals[mask]) 2331 as_bad (_("detected global register use not covered by .register pseudo-op")); 2332 2333 /* Got the register, now figure out where 2334 it goes in the opcode. */ 2335 switch (*args) 2336 { 2337 case '1': 2338 opcode |= mask << 14; 2339 continue; 2340 2341 case '2': 2342 opcode |= mask; 2343 continue; 2344 2345 case 'd': 2346 opcode |= mask << 25; 2347 continue; 2348 2349 case 'r': 2350 opcode |= (mask << 25) | (mask << 14); 2351 continue; 2352 2353 case 'O': 2354 opcode |= (mask << 25) | (mask << 0); 2355 continue; 2356 } 2357 } 2358 break; 2359 2360 case 'e': /* next operand is a floating point register */ 2361 case 'v': 2362 case 'V': 2363 2364 case 'f': 2365 case 'B': 2366 case 'R': 2367 2368 case '4': 2369 case '5': 2370 2371 case 'g': 2372 case 'H': 2373 case 'J': 2374 case '}': 2375 { 2376 char format; 2377 2378 if (*s++ == '%' 2379 && ((format = *s) == 'f') 2380 && ISDIGIT (*++s)) 2381 { 2382 for (mask = 0; ISDIGIT (*s); ++s) 2383 { 2384 mask = 10 * mask + (*s - '0'); 2385 } /* read the number */ 2386 2387 if ((*args == 'v' 2388 || *args == 'B' 2389 || *args == '5' 2390 || *args == 'H') 2391 && (mask & 1)) 2392 { 2393 break; 2394 } /* register must be even numbered */ 2395 2396 if ((*args == 'V' 2397 || *args == 'R' 2398 || *args == 'J') 2399 && (mask & 3)) 2400 { 2401 break; 2402 } /* register must be multiple of 4 */ 2403 2404 if (mask >= 64) 2405 { 2406 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2407 error_message = _(": There are only 64 f registers; [0-63]"); 2408 else 2409 error_message = _(": There are only 32 f registers; [0-31]"); 2410 goto error; 2411 } /* on error */ 2412 else if (mask >= 32) 2413 { 2414 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2415 { 2416 if (*args == 'e' || *args == 'f' || *args == 'g') 2417 { 2418 error_message 2419 = _(": There are only 32 single precision f registers; [0-31]"); 2420 goto error; 2421 } 2422 v9_arg_p = 1; 2423 mask -= 31; /* wrap high bit */ 2424 } 2425 else 2426 { 2427 error_message = _(": There are only 32 f registers; [0-31]"); 2428 goto error; 2429 } 2430 } 2431 } 2432 else 2433 { 2434 break; 2435 } /* if not an 'f' register. */ 2436 2437 if (*args == '}' && mask != RS2 (opcode)) 2438 { 2439 error_message 2440 = _(": Instruction requires frs2 and frsd must be the same register"); 2441 goto error; 2442 } 2443 2444 switch (*args) 2445 { 2446 case 'v': 2447 case 'V': 2448 case 'e': 2449 opcode |= RS1 (mask); 2450 continue; 2451 2452 case 'f': 2453 case 'B': 2454 case 'R': 2455 opcode |= RS2 (mask); 2456 continue; 2457 2458 case '4': 2459 case '5': 2460 opcode |= RS3 (mask); 2461 continue; 2462 2463 case 'g': 2464 case 'H': 2465 case 'J': 2466 case '}': 2467 opcode |= RD (mask); 2468 continue; 2469 } /* Pack it in. */ 2470 2471 know (0); 2472 break; 2473 } /* float arg */ 2474 2475 case 'F': 2476 if (strncmp (s, "%fsr", 4) == 0) 2477 { 2478 s += 4; 2479 continue; 2480 } 2481 break; 2482 2483 case '(': 2484 if (strncmp (s, "%efsr", 5) == 0) 2485 { 2486 s += 5; 2487 continue; 2488 } 2489 break; 2490 2491 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2492 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2493 goto immediate; 2494 2495 case 'l': /* 22 bit PC relative immediate */ 2496 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2497 the_insn.pcrel = 1; 2498 goto immediate; 2499 2500 case 'L': /* 30 bit immediate */ 2501 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2502 the_insn.pcrel = 1; 2503 goto immediate; 2504 2505 case 'h': 2506 case 'n': /* 22 bit immediate */ 2507 the_insn.reloc = BFD_RELOC_SPARC22; 2508 goto immediate; 2509 2510 case 'i': /* 13 bit immediate */ 2511 the_insn.reloc = BFD_RELOC_SPARC13; 2512 2513 /* fallthrough */ 2514 2515 immediate: 2516 if (*s == ' ') 2517 s++; 2518 2519 { 2520 char *s1; 2521 char *op_arg = NULL; 2522 static expressionS op_exp; 2523 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2524 2525 /* Check for %hi, etc. */ 2526 if (*s == '%') 2527 { 2528 static const struct ops { 2529 /* The name as it appears in assembler. */ 2530 char *name; 2531 /* strlen (name), precomputed for speed */ 2532 int len; 2533 /* The reloc this pseudo-op translates to. */ 2534 int reloc; 2535 /* Non-zero if for v9 only. */ 2536 int v9_p; 2537 /* Non-zero if can be used in pc-relative contexts. */ 2538 int pcrel_p;/*FIXME:wip*/ 2539 } ops[] = { 2540 /* hix/lox must appear before hi/lo so %hix won't be 2541 mistaken for %hi. */ 2542 { "hix", 3, BFD_RELOC_SPARC_HIX22, 1, 0 }, 2543 { "lox", 3, BFD_RELOC_SPARC_LOX10, 1, 0 }, 2544 { "hi", 2, BFD_RELOC_HI22, 0, 1 }, 2545 { "lo", 2, BFD_RELOC_LO10, 0, 1 }, 2546 { "pc22", 4, BFD_RELOC_SPARC_PC22, 0, 1 }, 2547 { "pc10", 4, BFD_RELOC_SPARC_PC10, 0, 1 }, 2548 { "hh", 2, BFD_RELOC_SPARC_HH22, 1, 1 }, 2549 { "hm", 2, BFD_RELOC_SPARC_HM10, 1, 1 }, 2550 { "lm", 2, BFD_RELOC_SPARC_LM22, 1, 1 }, 2551 { "h34", 3, BFD_RELOC_SPARC_H34, 1, 0 }, 2552 { "l34", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2553 { "h44", 3, BFD_RELOC_SPARC_H44, 1, 0 }, 2554 { "m44", 3, BFD_RELOC_SPARC_M44, 1, 0 }, 2555 { "l44", 3, BFD_RELOC_SPARC_L44, 1, 0 }, 2556 { "uhi", 3, BFD_RELOC_SPARC_HH22, 1, 0 }, 2557 { "ulo", 3, BFD_RELOC_SPARC_HM10, 1, 0 }, 2558 { "tgd_hi22", 8, BFD_RELOC_SPARC_TLS_GD_HI22, 0, 0 }, 2559 { "tgd_lo10", 8, BFD_RELOC_SPARC_TLS_GD_LO10, 0, 0 }, 2560 { "tldm_hi22", 9, BFD_RELOC_SPARC_TLS_LDM_HI22, 0, 0 }, 2561 { "tldm_lo10", 9, BFD_RELOC_SPARC_TLS_LDM_LO10, 0, 0 }, 2562 { "tldo_hix22", 10, BFD_RELOC_SPARC_TLS_LDO_HIX22, 0, 2563 0 }, 2564 { "tldo_lox10", 10, BFD_RELOC_SPARC_TLS_LDO_LOX10, 0, 2565 0 }, 2566 { "tie_hi22", 8, BFD_RELOC_SPARC_TLS_IE_HI22, 0, 0 }, 2567 { "tie_lo10", 8, BFD_RELOC_SPARC_TLS_IE_LO10, 0, 0 }, 2568 { "tle_hix22", 9, BFD_RELOC_SPARC_TLS_LE_HIX22, 0, 0 }, 2569 { "tle_lox10", 9, BFD_RELOC_SPARC_TLS_LE_LOX10, 0, 0 }, 2570 { "gdop_hix22", 10, BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 2571 0, 0 }, 2572 { "gdop_lox10", 10, BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 2573 0, 0 }, 2574 { NULL, 0, 0, 0, 0 } 2575 }; 2576 const struct ops *o; 2577 2578 for (o = ops; o->name; o++) 2579 if (strncmp (s + 1, o->name, o->len) == 0) 2580 break; 2581 if (o->name == NULL) 2582 break; 2583 2584 if (s[o->len + 1] != '(') 2585 { 2586 as_bad (_("Illegal operands: %%%s requires arguments in ()"), o->name); 2587 return special_case; 2588 } 2589 2590 op_arg = o->name; 2591 the_insn.reloc = o->reloc; 2592 s += o->len + 2; 2593 v9_arg_p = o->v9_p; 2594 } 2595 2596 /* Note that if the get_expression() fails, we will still 2597 have created U entries in the symbol table for the 2598 'symbols' in the input string. Try not to create U 2599 symbols for registers, etc. */ 2600 2601 /* This stuff checks to see if the expression ends in 2602 +%reg. If it does, it removes the register from 2603 the expression, and re-sets 's' to point to the 2604 right place. */ 2605 2606 if (op_arg) 2607 { 2608 int npar = 0; 2609 2610 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2611 if (*s1 == '(') 2612 npar++; 2613 else if (*s1 == ')') 2614 { 2615 if (!npar) 2616 break; 2617 npar--; 2618 } 2619 2620 if (*s1 != ')') 2621 { 2622 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2623 return special_case; 2624 } 2625 2626 *s1 = '\0'; 2627 (void) get_expression (s); 2628 *s1 = ')'; 2629 s = s1 + 1; 2630 if (*s == ',' || *s == ']' || !*s) 2631 continue; 2632 if (*s != '+' && *s != '-') 2633 { 2634 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2635 return special_case; 2636 } 2637 *s1 = '0'; 2638 s = s1; 2639 op_exp = the_insn.exp; 2640 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2641 } 2642 2643 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2644 ; 2645 2646 if (s1 != s && ISDIGIT (s1[-1])) 2647 { 2648 if (s1[-2] == '%' && s1[-3] == '+') 2649 s1 -= 3; 2650 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2651 s1 -= 4; 2652 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') 2653 s1 -= 5; 2654 else 2655 s1 = NULL; 2656 if (s1) 2657 { 2658 *s1 = '\0'; 2659 if (op_arg && s1 == s + 1) 2660 the_insn.exp.X_op = O_absent; 2661 else 2662 (void) get_expression (s); 2663 *s1 = '+'; 2664 if (op_arg) 2665 *s = ')'; 2666 s = s1; 2667 } 2668 } 2669 else 2670 s1 = NULL; 2671 2672 if (!s1) 2673 { 2674 (void) get_expression (s); 2675 if (op_arg) 2676 *s = ')'; 2677 s = expr_end; 2678 } 2679 2680 if (op_arg) 2681 { 2682 the_insn.exp2 = the_insn.exp; 2683 the_insn.exp = op_exp; 2684 if (the_insn.exp2.X_op == O_absent) 2685 the_insn.exp2.X_op = O_illegal; 2686 else if (the_insn.exp.X_op == O_absent) 2687 { 2688 the_insn.exp = the_insn.exp2; 2689 the_insn.exp2.X_op = O_illegal; 2690 } 2691 else if (the_insn.exp.X_op == O_constant) 2692 { 2693 valueT val = the_insn.exp.X_add_number; 2694 switch (the_insn.reloc) 2695 { 2696 default: 2697 break; 2698 2699 case BFD_RELOC_SPARC_HH22: 2700 val = BSR (val, 32); 2701 /* Fall through. */ 2702 2703 case BFD_RELOC_SPARC_LM22: 2704 case BFD_RELOC_HI22: 2705 val = (val >> 10) & 0x3fffff; 2706 break; 2707 2708 case BFD_RELOC_SPARC_HM10: 2709 val = BSR (val, 32); 2710 /* Fall through. */ 2711 2712 case BFD_RELOC_LO10: 2713 val &= 0x3ff; 2714 break; 2715 2716 case BFD_RELOC_SPARC_H34: 2717 val >>= 12; 2718 val &= 0x3fffff; 2719 break; 2720 2721 case BFD_RELOC_SPARC_H44: 2722 val >>= 22; 2723 val &= 0x3fffff; 2724 break; 2725 2726 case BFD_RELOC_SPARC_M44: 2727 val >>= 12; 2728 val &= 0x3ff; 2729 break; 2730 2731 case BFD_RELOC_SPARC_L44: 2732 val &= 0xfff; 2733 break; 2734 2735 case BFD_RELOC_SPARC_HIX22: 2736 val = ~val; 2737 val = (val >> 10) & 0x3fffff; 2738 break; 2739 2740 case BFD_RELOC_SPARC_LOX10: 2741 val = (val & 0x3ff) | 0x1c00; 2742 break; 2743 } 2744 the_insn.exp = the_insn.exp2; 2745 the_insn.exp.X_add_number += val; 2746 the_insn.exp2.X_op = O_illegal; 2747 the_insn.reloc = old_reloc; 2748 } 2749 else if (the_insn.exp2.X_op != O_constant) 2750 { 2751 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2752 return special_case; 2753 } 2754 else 2755 { 2756 if (old_reloc != BFD_RELOC_SPARC13 2757 || the_insn.reloc != BFD_RELOC_LO10 2758 || sparc_arch_size != 64 2759 || sparc_pic_code) 2760 { 2761 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2762 return special_case; 2763 } 2764 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2765 } 2766 } 2767 } 2768 /* Check for constants that don't require emitting a reloc. */ 2769 if (the_insn.exp.X_op == O_constant 2770 && the_insn.exp.X_add_symbol == 0 2771 && the_insn.exp.X_op_symbol == 0) 2772 { 2773 /* For pc-relative call instructions, we reject 2774 constants to get better code. */ 2775 if (the_insn.pcrel 2776 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2777 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2778 { 2779 error_message = _(": PC-relative operand can't be a constant"); 2780 goto error; 2781 } 2782 2783 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2784 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2785 { 2786 error_message = _(": TLS operand can't be a constant"); 2787 goto error; 2788 } 2789 2790 /* Constants that won't fit are checked in md_apply_fix 2791 and bfd_install_relocation. 2792 ??? It would be preferable to install the constants 2793 into the insn here and save having to create a fixS 2794 for each one. There already exists code to handle 2795 all the various cases (e.g. in md_apply_fix and 2796 bfd_install_relocation) so duplicating all that code 2797 here isn't right. */ 2798 2799 /* This is a special case to handle cbcond instructions 2800 properly, which can need two relocations. The first 2801 one is for the 5-bit immediate field and the latter 2802 is going to be for the WDISP10 branch part. We 2803 handle the R_SPARC_5 immediate directly here so that 2804 we don't need to add support for multiple relocations 2805 in one instruction just yet. */ 2806 if (the_insn.reloc == BFD_RELOC_SPARC_5) 2807 { 2808 valueT val = the_insn.exp.X_add_number; 2809 2810 if (! in_bitfield_range (val, 0x1f)) 2811 { 2812 error_message = _(": Immediate value in cbcond is out of range."); 2813 goto error; 2814 } 2815 opcode |= val & 0x1f; 2816 the_insn.reloc = BFD_RELOC_NONE; 2817 } 2818 } 2819 2820 continue; 2821 2822 case 'a': 2823 if (*s++ == 'a') 2824 { 2825 opcode |= ANNUL; 2826 continue; 2827 } 2828 break; 2829 2830 case 'A': 2831 { 2832 int asi = 0; 2833 2834 /* Parse an asi. */ 2835 if (*s == '#') 2836 { 2837 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2838 { 2839 error_message = _(": invalid ASI name"); 2840 goto error; 2841 } 2842 } 2843 else 2844 { 2845 if (! parse_const_expr_arg (&s, &asi)) 2846 { 2847 error_message = _(": invalid ASI expression"); 2848 goto error; 2849 } 2850 if (asi < 0 || asi > 255) 2851 { 2852 error_message = _(": invalid ASI number"); 2853 goto error; 2854 } 2855 } 2856 opcode |= ASI (asi); 2857 continue; 2858 } /* Alternate space. */ 2859 2860 case 'p': 2861 if (strncmp (s, "%psr", 4) == 0) 2862 { 2863 s += 4; 2864 continue; 2865 } 2866 break; 2867 2868 case 'q': /* Floating point queue. */ 2869 if (strncmp (s, "%fq", 3) == 0) 2870 { 2871 s += 3; 2872 continue; 2873 } 2874 break; 2875 2876 case 'Q': /* Coprocessor queue. */ 2877 if (strncmp (s, "%cq", 3) == 0) 2878 { 2879 s += 3; 2880 continue; 2881 } 2882 break; 2883 2884 case 'S': 2885 if (strcmp (str, "set") == 0 2886 || strcmp (str, "setuw") == 0) 2887 { 2888 special_case = SPECIAL_CASE_SET; 2889 continue; 2890 } 2891 else if (strcmp (str, "setsw") == 0) 2892 { 2893 special_case = SPECIAL_CASE_SETSW; 2894 continue; 2895 } 2896 else if (strcmp (str, "setx") == 0) 2897 { 2898 special_case = SPECIAL_CASE_SETX; 2899 continue; 2900 } 2901 else if (strncmp (str, "fdiv", 4) == 0) 2902 { 2903 special_case = SPECIAL_CASE_FDIV; 2904 continue; 2905 } 2906 break; 2907 2908 case 'o': 2909 if (strncmp (s, "%asi", 4) != 0) 2910 break; 2911 s += 4; 2912 continue; 2913 2914 case 's': 2915 if (strncmp (s, "%fprs", 5) != 0) 2916 break; 2917 s += 5; 2918 continue; 2919 2920 case '{': 2921 if (strncmp (s, "%mcdper",7) != 0) 2922 break; 2923 s += 7; 2924 continue; 2925 2926 case 'E': 2927 if (strncmp (s, "%ccr", 4) != 0) 2928 break; 2929 s += 4; 2930 continue; 2931 2932 case 't': 2933 if (strncmp (s, "%tbr", 4) != 0) 2934 break; 2935 s += 4; 2936 continue; 2937 2938 case 'w': 2939 if (strncmp (s, "%wim", 4) != 0) 2940 break; 2941 s += 4; 2942 continue; 2943 2944 case 'x': 2945 { 2946 char *push = input_line_pointer; 2947 expressionS e; 2948 2949 input_line_pointer = s; 2950 expression (&e); 2951 if (e.X_op == O_constant) 2952 { 2953 int n = e.X_add_number; 2954 if (n != e.X_add_number || (n & ~0x1ff) != 0) 2955 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 2956 else 2957 opcode |= e.X_add_number << 5; 2958 } 2959 else 2960 as_bad (_("non-immediate OPF operand, ignored")); 2961 s = input_line_pointer; 2962 input_line_pointer = push; 2963 continue; 2964 } 2965 2966 case 'y': 2967 if (strncmp (s, "%y", 2) != 0) 2968 break; 2969 s += 2; 2970 continue; 2971 2972 case 'u': 2973 case 'U': 2974 { 2975 /* Parse a sparclet cpreg. */ 2976 int cpreg; 2977 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 2978 { 2979 error_message = _(": invalid cpreg name"); 2980 goto error; 2981 } 2982 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 2983 continue; 2984 } 2985 2986 default: 2987 as_fatal (_("failed sanity check.")); 2988 } /* switch on arg code. */ 2989 2990 /* Break out of for() loop. */ 2991 break; 2992 } /* For each arg that we expect. */ 2993 2994 error: 2995 if (match == 0) 2996 { 2997 /* Args don't match. */ 2998 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 2999 && (insn->name == insn[1].name 3000 || !strcmp (insn->name, insn[1].name))) 3001 { 3002 ++insn; 3003 s = argsStart; 3004 continue; 3005 } 3006 else 3007 { 3008 as_bad (_("Illegal operands%s"), error_message); 3009 return special_case; 3010 } 3011 } 3012 else 3013 { 3014 /* We have a match. Now see if the architecture is OK. */ 3015 int needed_arch_mask = insn->architecture; 3016 bfd_uint64_t hwcaps 3017 = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; 3018 3019 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 3020 if (hwcaps) 3021 hwcap_seen |= hwcaps; 3022 #endif 3023 if (v9_arg_p) 3024 { 3025 needed_arch_mask &= 3026 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 3027 if (! needed_arch_mask) 3028 needed_arch_mask = 3029 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 3030 } 3031 3032 if (needed_arch_mask 3033 & SPARC_OPCODE_SUPPORTED (current_architecture)) 3034 /* OK. */ 3035 ; 3036 /* Can we bump up the architecture? */ 3037 else if (needed_arch_mask 3038 & SPARC_OPCODE_SUPPORTED (max_architecture)) 3039 { 3040 enum sparc_opcode_arch_val needed_architecture = 3041 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 3042 & needed_arch_mask); 3043 3044 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 3045 if (warn_on_bump 3046 && needed_architecture > warn_after_architecture) 3047 { 3048 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 3049 sparc_opcode_archs[current_architecture].name, 3050 sparc_opcode_archs[needed_architecture].name, 3051 str); 3052 warn_after_architecture = needed_architecture; 3053 } 3054 current_architecture = needed_architecture; 3055 hwcap_allowed |= hwcaps; 3056 } 3057 /* Conflict. */ 3058 /* ??? This seems to be a bit fragile. What if the next entry in 3059 the opcode table is the one we want and it is supported? 3060 It is possible to arrange the table today so that this can't 3061 happen but what about tomorrow? */ 3062 else 3063 { 3064 int arch, printed_one_p = 0; 3065 char *p; 3066 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 3067 3068 /* Create a list of the architectures that support the insn. */ 3069 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 3070 p = required_archs; 3071 arch = sparc_ffs (needed_arch_mask); 3072 while ((1 << arch) <= needed_arch_mask) 3073 { 3074 if ((1 << arch) & needed_arch_mask) 3075 { 3076 if (printed_one_p) 3077 *p++ = '|'; 3078 strcpy (p, sparc_opcode_archs[arch].name); 3079 p += strlen (p); 3080 printed_one_p = 1; 3081 } 3082 ++arch; 3083 } 3084 3085 as_bad (_("Architecture mismatch on \"%s\"."), str); 3086 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 3087 required_archs, 3088 sparc_opcode_archs[max_architecture].name); 3089 return special_case; 3090 } 3091 3092 /* Make sure the hwcaps used by the instruction are 3093 currently enabled. */ 3094 if (hwcaps & ~hwcap_allowed) 3095 { 3096 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); 3097 3098 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), 3099 hwcap_name, str); 3100 return special_case; 3101 } 3102 } /* If no match. */ 3103 3104 break; 3105 } /* Forever looking for a match. */ 3106 3107 the_insn.opcode = opcode; 3108 return special_case; 3109 } 3110 3111 /* Parse an argument that can be expressed as a keyword. 3112 (eg: #StoreStore or %ccfr). 3113 The result is a boolean indicating success. 3114 If successful, INPUT_POINTER is updated. */ 3115 3116 static int 3117 parse_keyword_arg (int (*lookup_fn) (const char *), 3118 char **input_pointerP, 3119 int *valueP) 3120 { 3121 int value; 3122 char c, *p, *q; 3123 3124 p = *input_pointerP; 3125 for (q = p + (*p == '#' || *p == '%'); 3126 ISALNUM (*q) || *q == '_'; 3127 ++q) 3128 continue; 3129 c = *q; 3130 *q = 0; 3131 value = (*lookup_fn) (p); 3132 *q = c; 3133 if (value == -1) 3134 return 0; 3135 *valueP = value; 3136 *input_pointerP = q; 3137 return 1; 3138 } 3139 3140 /* Parse an argument that is a constant expression. 3141 The result is a boolean indicating success. */ 3142 3143 static int 3144 parse_const_expr_arg (char **input_pointerP, int *valueP) 3145 { 3146 char *save = input_line_pointer; 3147 expressionS exp; 3148 3149 input_line_pointer = *input_pointerP; 3150 /* The next expression may be something other than a constant 3151 (say if we're not processing the right variant of the insn). 3152 Don't call expression unless we're sure it will succeed as it will 3153 signal an error (which we want to defer until later). */ 3154 /* FIXME: It might be better to define md_operand and have it recognize 3155 things like %asi, etc. but continuing that route through to the end 3156 is a lot of work. */ 3157 if (*input_line_pointer == '%') 3158 { 3159 input_line_pointer = save; 3160 return 0; 3161 } 3162 expression (&exp); 3163 *input_pointerP = input_line_pointer; 3164 input_line_pointer = save; 3165 if (exp.X_op != O_constant) 3166 return 0; 3167 *valueP = exp.X_add_number; 3168 return 1; 3169 } 3170 3171 /* Subroutine of sparc_ip to parse an expression. */ 3172 3173 static int 3174 get_expression (char *str) 3175 { 3176 char *save_in; 3177 segT seg; 3178 3179 save_in = input_line_pointer; 3180 input_line_pointer = str; 3181 seg = expression (&the_insn.exp); 3182 if (seg != absolute_section 3183 && seg != text_section 3184 && seg != data_section 3185 && seg != bss_section 3186 && seg != undefined_section) 3187 { 3188 the_insn.error = _("bad segment"); 3189 expr_end = input_line_pointer; 3190 input_line_pointer = save_in; 3191 return 1; 3192 } 3193 expr_end = input_line_pointer; 3194 input_line_pointer = save_in; 3195 return 0; 3196 } 3197 3198 /* Subroutine of md_assemble to output one insn. */ 3199 3200 static void 3201 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) 3202 { 3203 char *toP = frag_more (4); 3204 3205 /* Put out the opcode. */ 3206 if (INSN_BIG_ENDIAN) 3207 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); 3208 else 3209 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); 3210 3211 /* Put out the symbol-dependent stuff. */ 3212 if (theinsn->reloc != BFD_RELOC_NONE) 3213 { 3214 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 3215 (toP - frag_now->fr_literal), /* Where. */ 3216 4, /* Size. */ 3217 &theinsn->exp, 3218 theinsn->pcrel, 3219 theinsn->reloc); 3220 /* Turn off overflow checking in fixup_segment. We'll do our 3221 own overflow checking in md_apply_fix. This is necessary because 3222 the insn size is 4 and fixup_segment will signal an overflow for 3223 large 8 byte quantities. */ 3224 fixP->fx_no_overflow = 1; 3225 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) 3226 fixP->tc_fix_data = theinsn->exp2.X_add_number; 3227 } 3228 3229 last_insn = insn; 3230 last_opcode = theinsn->opcode; 3231 3232 #ifdef OBJ_ELF 3233 dwarf2_emit_insn (4); 3234 #endif 3235 } 3236 3237 char * 3239 md_atof (int type, char *litP, int *sizeP) 3240 { 3241 return ieee_md_atof (type, litP, sizeP, target_big_endian); 3242 } 3243 3244 /* Write a value out to the object file, using the appropriate 3245 endianness. */ 3246 3247 void 3248 md_number_to_chars (char *buf, valueT val, int n) 3249 { 3250 if (target_big_endian) 3251 number_to_chars_bigendian (buf, val, n); 3252 else if (target_little_endian_data 3253 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3254 /* Output debug words, which are not in allocated sections, as big 3255 endian. */ 3256 number_to_chars_bigendian (buf, val, n); 3257 else if (target_little_endian_data || ! target_big_endian) 3258 number_to_chars_littleendian (buf, val, n); 3259 } 3260 3261 /* Apply a fixS to the frags, now that we know the value it ought to 3263 hold. */ 3264 3265 void 3266 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) 3267 { 3268 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3269 offsetT val = * (offsetT *) valP; 3270 long insn; 3271 3272 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3273 3274 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3275 3276 #ifdef OBJ_ELF 3277 /* SPARC ELF relocations don't use an addend in the data field. */ 3278 if (fixP->fx_addsy != NULL) 3279 { 3280 switch (fixP->fx_r_type) 3281 { 3282 case BFD_RELOC_SPARC_TLS_GD_HI22: 3283 case BFD_RELOC_SPARC_TLS_GD_LO10: 3284 case BFD_RELOC_SPARC_TLS_GD_ADD: 3285 case BFD_RELOC_SPARC_TLS_GD_CALL: 3286 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3287 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3288 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3289 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3290 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3291 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3292 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3293 case BFD_RELOC_SPARC_TLS_IE_HI22: 3294 case BFD_RELOC_SPARC_TLS_IE_LO10: 3295 case BFD_RELOC_SPARC_TLS_IE_LD: 3296 case BFD_RELOC_SPARC_TLS_IE_LDX: 3297 case BFD_RELOC_SPARC_TLS_IE_ADD: 3298 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3299 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3300 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3301 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3302 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3303 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3304 case BFD_RELOC_SPARC_TLS_TPOFF32: 3305 case BFD_RELOC_SPARC_TLS_TPOFF64: 3306 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3307 3308 default: 3309 break; 3310 } 3311 3312 return; 3313 } 3314 #endif 3315 3316 /* This is a hack. There should be a better way to 3317 handle this. Probably in terms of howto fields, once 3318 we can look at these fixups in terms of howtos. */ 3319 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3320 val += fixP->fx_where + fixP->fx_frag->fr_address; 3321 3322 #ifdef OBJ_AOUT 3323 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3324 generate a reloc, then we just want to let the reloc addend set 3325 the value. We do not want to also stuff the addend into the 3326 object file. Including the addend in the object file works when 3327 doing a static link, because the linker will ignore the object 3328 file contents. However, the dynamic linker does not ignore the 3329 object file contents. */ 3330 if (fixP->fx_addsy != NULL 3331 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3332 val = 0; 3333 3334 /* When generating PIC code, we do not want an addend for a reloc 3335 against a local symbol. We adjust fx_addnumber to cancel out the 3336 value already included in val, and to also cancel out the 3337 adjustment which bfd_install_relocation will create. */ 3338 if (sparc_pic_code 3339 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3340 && fixP->fx_addsy != NULL 3341 && ! S_IS_COMMON (fixP->fx_addsy) 3342 && symbol_section_p (fixP->fx_addsy)) 3343 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3344 3345 /* When generating PIC code, we need to fiddle to get 3346 bfd_install_relocation to do the right thing for a PC relative 3347 reloc against a local symbol which we are going to keep. */ 3348 if (sparc_pic_code 3349 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3350 && fixP->fx_addsy != NULL 3351 && (S_IS_EXTERNAL (fixP->fx_addsy) 3352 || S_IS_WEAK (fixP->fx_addsy)) 3353 && S_IS_DEFINED (fixP->fx_addsy) 3354 && ! S_IS_COMMON (fixP->fx_addsy)) 3355 { 3356 val = 0; 3357 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3358 } 3359 #endif 3360 3361 /* If this is a data relocation, just output VAL. */ 3362 3363 if (fixP->fx_r_type == BFD_RELOC_8) 3364 { 3365 md_number_to_chars (buf, val, 1); 3366 } 3367 else if (fixP->fx_r_type == BFD_RELOC_16 3368 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3369 { 3370 md_number_to_chars (buf, val, 2); 3371 } 3372 else if (fixP->fx_r_type == BFD_RELOC_32 3373 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3374 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3375 { 3376 md_number_to_chars (buf, val, 4); 3377 } 3378 else if (fixP->fx_r_type == BFD_RELOC_64 3379 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3380 { 3381 md_number_to_chars (buf, val, 8); 3382 } 3383 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3384 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3385 { 3386 fixP->fx_done = 0; 3387 return; 3388 } 3389 else 3390 { 3391 /* It's a relocation against an instruction. */ 3392 3393 if (INSN_BIG_ENDIAN) 3394 insn = bfd_getb32 ((unsigned char *) buf); 3395 else 3396 insn = bfd_getl32 ((unsigned char *) buf); 3397 3398 switch (fixP->fx_r_type) 3399 { 3400 case BFD_RELOC_32_PCREL_S2: 3401 val = val >> 2; 3402 /* FIXME: This increment-by-one deserves a comment of why it's 3403 being done! */ 3404 if (! sparc_pic_code 3405 || fixP->fx_addsy == NULL 3406 || symbol_section_p (fixP->fx_addsy)) 3407 ++val; 3408 3409 insn |= val & 0x3fffffff; 3410 3411 /* See if we have a delay slot. */ 3412 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3413 { 3414 #define G0 0 3415 #define O7 15 3416 #define XCC (2 << 20) 3417 #define COND(x) (((x)&0xf)<<25) 3418 #define CONDA COND(0x8) 3419 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3420 #define INSN_BA (F2(0,2) | CONDA) 3421 #define INSN_OR F3(2, 0x2, 0) 3422 #define INSN_NOP F2(0,4) 3423 3424 long delay; 3425 3426 /* If the instruction is a call with either: 3427 restore 3428 arithmetic instruction with rd == %o7 3429 where rs1 != %o7 and rs2 if it is register != %o7 3430 then we can optimize if the call destination is near 3431 by changing the call into a branch always. */ 3432 if (INSN_BIG_ENDIAN) 3433 delay = bfd_getb32 ((unsigned char *) buf + 4); 3434 else 3435 delay = bfd_getl32 ((unsigned char *) buf + 4); 3436 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3437 break; 3438 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3439 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3440 || ((delay & RD (~0)) != RD (O7)))) 3441 break; 3442 if ((delay & RS1 (~0)) == RS1 (O7) 3443 || ((delay & F3I (~0)) == 0 3444 && (delay & RS2 (~0)) == RS2 (O7))) 3445 break; 3446 /* Ensure the branch will fit into simm22. */ 3447 if ((val & 0x3fe00000) 3448 && (val & 0x3fe00000) != 0x3fe00000) 3449 break; 3450 /* Check if the arch is v9 and branch will fit 3451 into simm19. */ 3452 if (((val & 0x3c0000) == 0 3453 || (val & 0x3c0000) == 0x3c0000) 3454 && (sparc_arch_size == 64 3455 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3456 /* ba,pt %xcc */ 3457 insn = INSN_BPA | (val & 0x7ffff); 3458 else 3459 /* ba */ 3460 insn = INSN_BA | (val & 0x3fffff); 3461 if (fixP->fx_where >= 4 3462 && ((delay & (0xffffffff ^ RS1 (~0))) 3463 == (INSN_OR | RD (O7) | RS2 (G0)))) 3464 { 3465 long setter; 3466 int reg; 3467 3468 if (INSN_BIG_ENDIAN) 3469 setter = bfd_getb32 ((unsigned char *) buf - 4); 3470 else 3471 setter = bfd_getl32 ((unsigned char *) buf - 4); 3472 if ((setter & (0xffffffff ^ RD (~0))) 3473 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3474 break; 3475 /* The sequence was 3476 or %o7, %g0, %rN 3477 call foo 3478 or %rN, %g0, %o7 3479 3480 If call foo was replaced with ba, replace 3481 or %rN, %g0, %o7 with nop. */ 3482 reg = (delay & RS1 (~0)) >> 14; 3483 if (reg != ((setter & RD (~0)) >> 25) 3484 || reg == G0 || reg == O7) 3485 break; 3486 3487 if (INSN_BIG_ENDIAN) 3488 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3489 else 3490 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3491 } 3492 } 3493 break; 3494 3495 case BFD_RELOC_SPARC_11: 3496 if (! in_signed_range (val, 0x7ff)) 3497 as_bad_where (fixP->fx_file, fixP->fx_line, 3498 _("relocation overflow")); 3499 insn |= val & 0x7ff; 3500 break; 3501 3502 case BFD_RELOC_SPARC_10: 3503 if (! in_signed_range (val, 0x3ff)) 3504 as_bad_where (fixP->fx_file, fixP->fx_line, 3505 _("relocation overflow")); 3506 insn |= val & 0x3ff; 3507 break; 3508 3509 case BFD_RELOC_SPARC_7: 3510 if (! in_bitfield_range (val, 0x7f)) 3511 as_bad_where (fixP->fx_file, fixP->fx_line, 3512 _("relocation overflow")); 3513 insn |= val & 0x7f; 3514 break; 3515 3516 case BFD_RELOC_SPARC_6: 3517 if (! in_bitfield_range (val, 0x3f)) 3518 as_bad_where (fixP->fx_file, fixP->fx_line, 3519 _("relocation overflow")); 3520 insn |= val & 0x3f; 3521 break; 3522 3523 case BFD_RELOC_SPARC_5: 3524 if (! in_bitfield_range (val, 0x1f)) 3525 as_bad_where (fixP->fx_file, fixP->fx_line, 3526 _("relocation overflow")); 3527 insn |= val & 0x1f; 3528 break; 3529 3530 case BFD_RELOC_SPARC_WDISP10: 3531 if ((val & 3) 3532 || val >= 0x007fc 3533 || val <= -(offsetT) 0x808) 3534 as_bad_where (fixP->fx_file, fixP->fx_line, 3535 _("relocation overflow")); 3536 /* FIXME: The +1 deserves a comment. */ 3537 val = (val >> 2) + 1; 3538 insn |= ((val & 0x300) << 11) 3539 | ((val & 0xff) << 5); 3540 break; 3541 3542 case BFD_RELOC_SPARC_WDISP16: 3543 if ((val & 3) 3544 || val >= 0x1fffc 3545 || val <= -(offsetT) 0x20008) 3546 as_bad_where (fixP->fx_file, fixP->fx_line, 3547 _("relocation overflow")); 3548 /* FIXME: The +1 deserves a comment. */ 3549 val = (val >> 2) + 1; 3550 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3551 break; 3552 3553 case BFD_RELOC_SPARC_WDISP19: 3554 if ((val & 3) 3555 || val >= 0xffffc 3556 || val <= -(offsetT) 0x100008) 3557 as_bad_where (fixP->fx_file, fixP->fx_line, 3558 _("relocation overflow")); 3559 /* FIXME: The +1 deserves a comment. */ 3560 val = (val >> 2) + 1; 3561 insn |= val & 0x7ffff; 3562 break; 3563 3564 case BFD_RELOC_SPARC_HH22: 3565 val = BSR (val, 32); 3566 /* Fall through. */ 3567 3568 case BFD_RELOC_SPARC_LM22: 3569 case BFD_RELOC_HI22: 3570 if (!fixP->fx_addsy) 3571 insn |= (val >> 10) & 0x3fffff; 3572 else 3573 /* FIXME: Need comment explaining why we do this. */ 3574 insn &= ~0xffff; 3575 break; 3576 3577 case BFD_RELOC_SPARC22: 3578 if (val & ~0x003fffff) 3579 as_bad_where (fixP->fx_file, fixP->fx_line, 3580 _("relocation overflow")); 3581 insn |= (val & 0x3fffff); 3582 break; 3583 3584 case BFD_RELOC_SPARC_HM10: 3585 val = BSR (val, 32); 3586 /* Fall through. */ 3587 3588 case BFD_RELOC_LO10: 3589 if (!fixP->fx_addsy) 3590 insn |= val & 0x3ff; 3591 else 3592 /* FIXME: Need comment explaining why we do this. */ 3593 insn &= ~0xff; 3594 break; 3595 3596 case BFD_RELOC_SPARC_OLO10: 3597 val &= 0x3ff; 3598 val += fixP->tc_fix_data; 3599 /* Fall through. */ 3600 3601 case BFD_RELOC_SPARC13: 3602 if (! in_signed_range (val, 0x1fff)) 3603 as_bad_where (fixP->fx_file, fixP->fx_line, 3604 _("relocation overflow")); 3605 insn |= val & 0x1fff; 3606 break; 3607 3608 case BFD_RELOC_SPARC_WDISP22: 3609 val = (val >> 2) + 1; 3610 /* Fall through. */ 3611 case BFD_RELOC_SPARC_BASE22: 3612 insn |= val & 0x3fffff; 3613 break; 3614 3615 case BFD_RELOC_SPARC_H34: 3616 if (!fixP->fx_addsy) 3617 { 3618 bfd_vma tval = val; 3619 tval >>= 12; 3620 insn |= tval & 0x3fffff; 3621 } 3622 break; 3623 3624 case BFD_RELOC_SPARC_H44: 3625 if (!fixP->fx_addsy) 3626 { 3627 bfd_vma tval = val; 3628 tval >>= 22; 3629 insn |= tval & 0x3fffff; 3630 } 3631 break; 3632 3633 case BFD_RELOC_SPARC_M44: 3634 if (!fixP->fx_addsy) 3635 insn |= (val >> 12) & 0x3ff; 3636 break; 3637 3638 case BFD_RELOC_SPARC_L44: 3639 if (!fixP->fx_addsy) 3640 insn |= val & 0xfff; 3641 break; 3642 3643 case BFD_RELOC_SPARC_HIX22: 3644 if (!fixP->fx_addsy) 3645 { 3646 val ^= ~(offsetT) 0; 3647 insn |= (val >> 10) & 0x3fffff; 3648 } 3649 break; 3650 3651 case BFD_RELOC_SPARC_LOX10: 3652 if (!fixP->fx_addsy) 3653 insn |= 0x1c00 | (val & 0x3ff); 3654 break; 3655 3656 case BFD_RELOC_NONE: 3657 default: 3658 as_bad_where (fixP->fx_file, fixP->fx_line, 3659 _("bad or unhandled relocation type: 0x%02x"), 3660 fixP->fx_r_type); 3661 break; 3662 } 3663 3664 if (INSN_BIG_ENDIAN) 3665 bfd_putb32 (insn, (unsigned char *) buf); 3666 else 3667 bfd_putl32 (insn, (unsigned char *) buf); 3668 } 3669 3670 /* Are we finished with this relocation now? */ 3671 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3672 fixP->fx_done = 1; 3673 } 3674 3675 /* Translate internal representation of relocation info to BFD target 3676 format. */ 3677 3678 arelent ** 3679 tc_gen_reloc (asection *section, fixS *fixp) 3680 { 3681 static arelent *relocs[3]; 3682 arelent *reloc; 3683 bfd_reloc_code_real_type code; 3684 3685 relocs[0] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3686 relocs[1] = NULL; 3687 3688 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3689 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3690 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3691 3692 switch (fixp->fx_r_type) 3693 { 3694 case BFD_RELOC_16: 3695 case BFD_RELOC_32: 3696 case BFD_RELOC_HI22: 3697 case BFD_RELOC_LO10: 3698 case BFD_RELOC_32_PCREL_S2: 3699 case BFD_RELOC_SPARC13: 3700 case BFD_RELOC_SPARC22: 3701 case BFD_RELOC_SPARC_PC22: 3702 case BFD_RELOC_SPARC_PC10: 3703 case BFD_RELOC_SPARC_BASE13: 3704 case BFD_RELOC_SPARC_WDISP10: 3705 case BFD_RELOC_SPARC_WDISP16: 3706 case BFD_RELOC_SPARC_WDISP19: 3707 case BFD_RELOC_SPARC_WDISP22: 3708 case BFD_RELOC_64: 3709 case BFD_RELOC_SPARC_5: 3710 case BFD_RELOC_SPARC_6: 3711 case BFD_RELOC_SPARC_7: 3712 case BFD_RELOC_SPARC_10: 3713 case BFD_RELOC_SPARC_11: 3714 case BFD_RELOC_SPARC_HH22: 3715 case BFD_RELOC_SPARC_HM10: 3716 case BFD_RELOC_SPARC_LM22: 3717 case BFD_RELOC_SPARC_PC_HH22: 3718 case BFD_RELOC_SPARC_PC_HM10: 3719 case BFD_RELOC_SPARC_PC_LM22: 3720 case BFD_RELOC_SPARC_H34: 3721 case BFD_RELOC_SPARC_H44: 3722 case BFD_RELOC_SPARC_M44: 3723 case BFD_RELOC_SPARC_L44: 3724 case BFD_RELOC_SPARC_HIX22: 3725 case BFD_RELOC_SPARC_LOX10: 3726 case BFD_RELOC_SPARC_REV32: 3727 case BFD_RELOC_SPARC_OLO10: 3728 case BFD_RELOC_SPARC_UA16: 3729 case BFD_RELOC_SPARC_UA32: 3730 case BFD_RELOC_SPARC_UA64: 3731 case BFD_RELOC_8_PCREL: 3732 case BFD_RELOC_16_PCREL: 3733 case BFD_RELOC_32_PCREL: 3734 case BFD_RELOC_64_PCREL: 3735 case BFD_RELOC_SPARC_PLT32: 3736 case BFD_RELOC_SPARC_PLT64: 3737 case BFD_RELOC_VTABLE_ENTRY: 3738 case BFD_RELOC_VTABLE_INHERIT: 3739 case BFD_RELOC_SPARC_TLS_GD_HI22: 3740 case BFD_RELOC_SPARC_TLS_GD_LO10: 3741 case BFD_RELOC_SPARC_TLS_GD_ADD: 3742 case BFD_RELOC_SPARC_TLS_GD_CALL: 3743 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3744 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3745 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3746 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3747 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3748 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3749 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3750 case BFD_RELOC_SPARC_TLS_IE_HI22: 3751 case BFD_RELOC_SPARC_TLS_IE_LO10: 3752 case BFD_RELOC_SPARC_TLS_IE_LD: 3753 case BFD_RELOC_SPARC_TLS_IE_LDX: 3754 case BFD_RELOC_SPARC_TLS_IE_ADD: 3755 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3756 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3757 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3758 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3759 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: 3760 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: 3761 case BFD_RELOC_SPARC_GOTDATA_OP: 3762 code = fixp->fx_r_type; 3763 break; 3764 default: 3765 abort (); 3766 return NULL; 3767 } 3768 3769 #if defined (OBJ_ELF) || defined (OBJ_AOUT) 3770 /* If we are generating PIC code, we need to generate a different 3771 set of relocs. */ 3772 3773 #ifdef OBJ_ELF 3774 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3775 #else 3776 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3777 #endif 3778 #ifdef TE_VXWORKS 3779 #define GOTT_BASE "__GOTT_BASE__" 3780 #define GOTT_INDEX "__GOTT_INDEX__" 3781 #endif 3782 3783 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3784 3785 if (sparc_pic_code) 3786 { 3787 switch (code) 3788 { 3789 case BFD_RELOC_32_PCREL_S2: 3790 if (generic_force_reloc (fixp)) 3791 code = BFD_RELOC_SPARC_WPLT30; 3792 break; 3793 case BFD_RELOC_HI22: 3794 code = BFD_RELOC_SPARC_GOT22; 3795 if (fixp->fx_addsy != NULL) 3796 { 3797 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3798 code = BFD_RELOC_SPARC_PC22; 3799 #ifdef TE_VXWORKS 3800 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3801 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3802 code = BFD_RELOC_HI22; /* Unchanged. */ 3803 #endif 3804 } 3805 break; 3806 case BFD_RELOC_LO10: 3807 code = BFD_RELOC_SPARC_GOT10; 3808 if (fixp->fx_addsy != NULL) 3809 { 3810 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3811 code = BFD_RELOC_SPARC_PC10; 3812 #ifdef TE_VXWORKS 3813 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3814 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3815 code = BFD_RELOC_LO10; /* Unchanged. */ 3816 #endif 3817 } 3818 break; 3819 case BFD_RELOC_SPARC13: 3820 code = BFD_RELOC_SPARC_GOT13; 3821 break; 3822 default: 3823 break; 3824 } 3825 } 3826 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3827 3828 /* Nothing is aligned in DWARF debugging sections. */ 3829 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) 3830 switch (code) 3831 { 3832 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; 3833 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; 3834 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; 3835 default: break; 3836 } 3837 3838 if (code == BFD_RELOC_SPARC_OLO10) 3839 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3840 else 3841 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3842 if (reloc->howto == 0) 3843 { 3844 as_bad_where (fixp->fx_file, fixp->fx_line, 3845 _("internal error: can't export reloc type %d (`%s')"), 3846 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3847 xfree (reloc); 3848 relocs[0] = NULL; 3849 return relocs; 3850 } 3851 3852 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3853 #ifdef OBJ_AOUT 3854 3855 if (reloc->howto->pc_relative == 0 3856 || code == BFD_RELOC_SPARC_PC10 3857 || code == BFD_RELOC_SPARC_PC22) 3858 reloc->addend = fixp->fx_addnumber; 3859 else if (sparc_pic_code 3860 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3861 && fixp->fx_addsy != NULL 3862 && (S_IS_EXTERNAL (fixp->fx_addsy) 3863 || S_IS_WEAK (fixp->fx_addsy)) 3864 && S_IS_DEFINED (fixp->fx_addsy) 3865 && ! S_IS_COMMON (fixp->fx_addsy)) 3866 reloc->addend = fixp->fx_addnumber; 3867 else 3868 reloc->addend = fixp->fx_offset - reloc->address; 3869 3870 #else /* elf or coff */ 3871 3872 if (code != BFD_RELOC_32_PCREL_S2 3873 && code != BFD_RELOC_SPARC_WDISP22 3874 && code != BFD_RELOC_SPARC_WDISP16 3875 && code != BFD_RELOC_SPARC_WDISP19 3876 && code != BFD_RELOC_SPARC_WDISP10 3877 && code != BFD_RELOC_SPARC_WPLT30 3878 && code != BFD_RELOC_SPARC_TLS_GD_CALL 3879 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 3880 reloc->addend = fixp->fx_addnumber; 3881 else if (symbol_section_p (fixp->fx_addsy)) 3882 reloc->addend = (section->vma 3883 + fixp->fx_addnumber 3884 + md_pcrel_from (fixp)); 3885 else 3886 reloc->addend = fixp->fx_offset; 3887 #endif 3888 3889 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 3890 on the same location. */ 3891 if (code == BFD_RELOC_SPARC_OLO10) 3892 { 3893 relocs[1] = reloc = (arelent *) xmalloc (sizeof (arelent)); 3894 relocs[2] = NULL; 3895 3896 reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); 3897 *reloc->sym_ptr_ptr 3898 = symbol_get_bfdsym (section_symbol (absolute_section)); 3899 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3900 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 3901 reloc->addend = fixp->tc_fix_data; 3902 } 3903 3904 return relocs; 3905 } 3906 3907 /* We have no need to default values of symbols. */ 3909 3910 symbolS * 3911 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 3912 { 3913 return 0; 3914 } 3915 3916 /* Round up a section size to the appropriate boundary. */ 3917 3918 valueT 3919 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 3920 { 3921 #ifndef OBJ_ELF 3922 /* This is not right for ELF; a.out wants it, and COFF will force 3923 the alignment anyways. */ 3924 valueT align = ((valueT) 1 3925 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 3926 valueT newsize; 3927 3928 /* Turn alignment value into a mask. */ 3929 align--; 3930 newsize = (size + align) & ~align; 3931 return newsize; 3932 #else 3933 return size; 3934 #endif 3935 } 3936 3937 /* Exactly what point is a PC-relative offset relative TO? 3938 On the sparc, they're relative to the address of the offset, plus 3939 its size. This gets us to the following instruction. 3940 (??? Is this right? FIXME-SOON) */ 3941 long 3942 md_pcrel_from (fixS *fixP) 3943 { 3944 long ret; 3945 3946 ret = fixP->fx_where + fixP->fx_frag->fr_address; 3947 if (! sparc_pic_code 3948 || fixP->fx_addsy == NULL 3949 || symbol_section_p (fixP->fx_addsy)) 3950 ret += fixP->fx_size; 3951 return ret; 3952 } 3953 3954 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 3956 of two. */ 3957 3958 static int 3959 mylog2 (int value) 3960 { 3961 int shift; 3962 3963 if (value <= 0) 3964 return -1; 3965 3966 for (shift = 0; (value & 1) == 0; value >>= 1) 3967 ++shift; 3968 3969 return (value == 1) ? shift : -1; 3970 } 3971 3972 /* Sort of like s_lcomm. */ 3973 3974 #ifndef OBJ_ELF 3975 static int max_alignment = 15; 3976 #endif 3977 3978 static void 3979 s_reserve (int ignore ATTRIBUTE_UNUSED) 3980 { 3981 char *name; 3982 char *p; 3983 char c; 3984 int align; 3985 int size; 3986 int temp; 3987 symbolS *symbolP; 3988 3989 name = input_line_pointer; 3990 c = get_symbol_end (); 3991 p = input_line_pointer; 3992 *p = c; 3993 SKIP_WHITESPACE (); 3994 3995 if (*input_line_pointer != ',') 3996 { 3997 as_bad (_("Expected comma after name")); 3998 ignore_rest_of_line (); 3999 return; 4000 } 4001 4002 ++input_line_pointer; 4003 4004 if ((size = get_absolute_expression ()) < 0) 4005 { 4006 as_bad (_("BSS length (%d.) <0! Ignored."), size); 4007 ignore_rest_of_line (); 4008 return; 4009 } /* Bad length. */ 4010 4011 *p = 0; 4012 symbolP = symbol_find_or_make (name); 4013 *p = c; 4014 4015 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 4016 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 4017 { 4018 as_bad (_("bad .reserve segment -- expected BSS segment")); 4019 return; 4020 } 4021 4022 if (input_line_pointer[2] == '.') 4023 input_line_pointer += 7; 4024 else 4025 input_line_pointer += 6; 4026 SKIP_WHITESPACE (); 4027 4028 if (*input_line_pointer == ',') 4029 { 4030 ++input_line_pointer; 4031 4032 SKIP_WHITESPACE (); 4033 if (*input_line_pointer == '\n') 4034 { 4035 as_bad (_("missing alignment")); 4036 ignore_rest_of_line (); 4037 return; 4038 } 4039 4040 align = (int) get_absolute_expression (); 4041 4042 #ifndef OBJ_ELF 4043 if (align > max_alignment) 4044 { 4045 align = max_alignment; 4046 as_warn (_("alignment too large; assuming %d"), align); 4047 } 4048 #endif 4049 4050 if (align < 0) 4051 { 4052 as_bad (_("negative alignment")); 4053 ignore_rest_of_line (); 4054 return; 4055 } 4056 4057 if (align != 0) 4058 { 4059 temp = mylog2 (align); 4060 if (temp < 0) 4061 { 4062 as_bad (_("alignment not a power of 2")); 4063 ignore_rest_of_line (); 4064 return; 4065 } 4066 4067 align = temp; 4068 } 4069 4070 record_alignment (bss_section, align); 4071 } 4072 else 4073 align = 0; 4074 4075 if (!S_IS_DEFINED (symbolP) 4076 #ifdef OBJ_AOUT 4077 && S_GET_OTHER (symbolP) == 0 4078 && S_GET_DESC (symbolP) == 0 4079 #endif 4080 ) 4081 { 4082 if (! need_pass_2) 4083 { 4084 char *pfrag; 4085 segT current_seg = now_seg; 4086 subsegT current_subseg = now_subseg; 4087 4088 /* Switch to bss. */ 4089 subseg_set (bss_section, 1); 4090 4091 if (align) 4092 /* Do alignment. */ 4093 frag_align (align, 0, 0); 4094 4095 /* Detach from old frag. */ 4096 if (S_GET_SEGMENT (symbolP) == bss_section) 4097 symbol_get_frag (symbolP)->fr_symbol = NULL; 4098 4099 symbol_set_frag (symbolP, frag_now); 4100 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4101 (offsetT) size, (char *) 0); 4102 *pfrag = 0; 4103 4104 S_SET_SEGMENT (symbolP, bss_section); 4105 4106 subseg_set (current_seg, current_subseg); 4107 4108 #ifdef OBJ_ELF 4109 S_SET_SIZE (symbolP, size); 4110 #endif 4111 } 4112 } 4113 else 4114 { 4115 as_warn (_("Ignoring attempt to re-define symbol %s"), 4116 S_GET_NAME (symbolP)); 4117 } 4118 4119 demand_empty_rest_of_line (); 4120 } 4121 4122 static void 4123 s_common (int ignore ATTRIBUTE_UNUSED) 4124 { 4125 char *name; 4126 char c; 4127 char *p; 4128 offsetT temp, size; 4129 symbolS *symbolP; 4130 4131 name = input_line_pointer; 4132 c = get_symbol_end (); 4133 /* Just after name is now '\0'. */ 4134 p = input_line_pointer; 4135 *p = c; 4136 SKIP_WHITESPACE (); 4137 if (*input_line_pointer != ',') 4138 { 4139 as_bad (_("Expected comma after symbol-name")); 4140 ignore_rest_of_line (); 4141 return; 4142 } 4143 4144 /* Skip ','. */ 4145 input_line_pointer++; 4146 4147 if ((temp = get_absolute_expression ()) < 0) 4148 { 4149 as_bad (_(".COMMon length (%lu) out of range ignored"), 4150 (unsigned long) temp); 4151 ignore_rest_of_line (); 4152 return; 4153 } 4154 size = temp; 4155 *p = 0; 4156 symbolP = symbol_find_or_make (name); 4157 *p = c; 4158 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 4159 { 4160 as_bad (_("Ignoring attempt to re-define symbol")); 4161 ignore_rest_of_line (); 4162 return; 4163 } 4164 if (S_GET_VALUE (symbolP) != 0) 4165 { 4166 if (S_GET_VALUE (symbolP) != (valueT) size) 4167 { 4168 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 4169 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 4170 } 4171 } 4172 else 4173 { 4174 #ifndef OBJ_ELF 4175 S_SET_VALUE (symbolP, (valueT) size); 4176 S_SET_EXTERNAL (symbolP); 4177 #endif 4178 } 4179 know (symbol_get_frag (symbolP) == &zero_address_frag); 4180 if (*input_line_pointer != ',') 4181 { 4182 as_bad (_("Expected comma after common length")); 4183 ignore_rest_of_line (); 4184 return; 4185 } 4186 input_line_pointer++; 4187 SKIP_WHITESPACE (); 4188 if (*input_line_pointer != '"') 4189 { 4190 temp = get_absolute_expression (); 4191 4192 #ifndef OBJ_ELF 4193 if (temp > max_alignment) 4194 { 4195 temp = max_alignment; 4196 as_warn (_("alignment too large; assuming %ld"), (long) temp); 4197 } 4198 #endif 4199 4200 if (temp < 0) 4201 { 4202 as_bad (_("negative alignment")); 4203 ignore_rest_of_line (); 4204 return; 4205 } 4206 4207 #ifdef OBJ_ELF 4208 if (symbol_get_obj (symbolP)->local) 4209 { 4210 segT old_sec; 4211 int old_subsec; 4212 int align; 4213 4214 old_sec = now_seg; 4215 old_subsec = now_subseg; 4216 4217 if (temp == 0) 4218 align = 0; 4219 else 4220 align = mylog2 (temp); 4221 4222 if (align < 0) 4223 { 4224 as_bad (_("alignment not a power of 2")); 4225 ignore_rest_of_line (); 4226 return; 4227 } 4228 4229 record_alignment (bss_section, align); 4230 subseg_set (bss_section, 0); 4231 if (align) 4232 frag_align (align, 0, 0); 4233 if (S_GET_SEGMENT (symbolP) == bss_section) 4234 symbol_get_frag (symbolP)->fr_symbol = 0; 4235 symbol_set_frag (symbolP, frag_now); 4236 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4237 (offsetT) size, (char *) 0); 4238 *p = 0; 4239 S_SET_SEGMENT (symbolP, bss_section); 4240 S_CLEAR_EXTERNAL (symbolP); 4241 S_SET_SIZE (symbolP, size); 4242 subseg_set (old_sec, old_subsec); 4243 } 4244 else 4245 #endif /* OBJ_ELF */ 4246 { 4247 allocate_common: 4248 S_SET_VALUE (symbolP, (valueT) size); 4249 #ifdef OBJ_ELF 4250 S_SET_ALIGN (symbolP, temp); 4251 S_SET_SIZE (symbolP, size); 4252 #endif 4253 S_SET_EXTERNAL (symbolP); 4254 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 4255 } 4256 } 4257 else 4258 { 4259 input_line_pointer++; 4260 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4261 if (*input_line_pointer == '.') 4262 input_line_pointer++; 4263 /* @@ Some say data, some say bss. */ 4264 if (strncmp (input_line_pointer, "bss\"", 4) 4265 && strncmp (input_line_pointer, "data\"", 5)) 4266 { 4267 while (*--input_line_pointer != '"') 4268 ; 4269 input_line_pointer--; 4270 goto bad_common_segment; 4271 } 4272 while (*input_line_pointer++ != '"') 4273 ; 4274 goto allocate_common; 4275 } 4276 4277 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4278 4279 demand_empty_rest_of_line (); 4280 return; 4281 4282 { 4283 bad_common_segment: 4284 p = input_line_pointer; 4285 while (*p && *p != '\n') 4286 p++; 4287 c = *p; 4288 *p = '\0'; 4289 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4290 *p = c; 4291 input_line_pointer = p; 4292 ignore_rest_of_line (); 4293 return; 4294 } 4295 } 4296 4297 /* Handle the .empty pseudo-op. This suppresses the warnings about 4298 invalid delay slot usage. */ 4299 4300 static void 4301 s_empty (int ignore ATTRIBUTE_UNUSED) 4302 { 4303 /* The easy way to implement is to just forget about the last 4304 instruction. */ 4305 last_insn = NULL; 4306 } 4307 4308 static void 4309 s_seg (int ignore ATTRIBUTE_UNUSED) 4310 { 4311 4312 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4313 { 4314 input_line_pointer += 6; 4315 s_text (0); 4316 return; 4317 } 4318 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4319 { 4320 input_line_pointer += 6; 4321 s_data (0); 4322 return; 4323 } 4324 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4325 { 4326 input_line_pointer += 7; 4327 s_data1 (); 4328 return; 4329 } 4330 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4331 { 4332 input_line_pointer += 5; 4333 /* We only support 2 segments -- text and data -- for now, so 4334 things in the "bss segment" will have to go into data for now. 4335 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4336 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4337 return; 4338 } 4339 as_bad (_("Unknown segment type")); 4340 demand_empty_rest_of_line (); 4341 } 4342 4343 static void 4344 s_data1 (void) 4345 { 4346 subseg_set (data_section, 1); 4347 demand_empty_rest_of_line (); 4348 } 4349 4350 static void 4351 s_proc (int ignore ATTRIBUTE_UNUSED) 4352 { 4353 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4354 { 4355 ++input_line_pointer; 4356 } 4357 ++input_line_pointer; 4358 } 4359 4360 /* This static variable is set by s_uacons to tell sparc_cons_align 4361 that the expression does not need to be aligned. */ 4362 4363 static int sparc_no_align_cons = 0; 4364 4365 /* This handles the unaligned space allocation pseudo-ops, such as 4366 .uaword. .uaword is just like .word, but the value does not need 4367 to be aligned. */ 4368 4369 static void 4370 s_uacons (int bytes) 4371 { 4372 /* Tell sparc_cons_align not to align this value. */ 4373 sparc_no_align_cons = 1; 4374 cons (bytes); 4375 sparc_no_align_cons = 0; 4376 } 4377 4378 /* This handles the native word allocation pseudo-op .nword. 4379 For sparc_arch_size 32 it is equivalent to .word, for 4380 sparc_arch_size 64 it is equivalent to .xword. */ 4381 4382 static void 4383 s_ncons (int bytes ATTRIBUTE_UNUSED) 4384 { 4385 cons (sparc_arch_size == 32 ? 4 : 8); 4386 } 4387 4388 #ifdef OBJ_ELF 4389 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4390 global register. 4391 The syntax is: 4392 4393 .register %g[2367],{#scratch|symbolname|#ignore} 4394 */ 4395 4396 static void 4397 s_register (int ignore ATTRIBUTE_UNUSED) 4398 { 4399 char c; 4400 int reg; 4401 int flags; 4402 const char *regname; 4403 4404 if (input_line_pointer[0] != '%' 4405 || input_line_pointer[1] != 'g' 4406 || ((input_line_pointer[2] & ~1) != '2' 4407 && (input_line_pointer[2] & ~1) != '6') 4408 || input_line_pointer[3] != ',') 4409 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4410 reg = input_line_pointer[2] - '0'; 4411 input_line_pointer += 4; 4412 4413 if (*input_line_pointer == '#') 4414 { 4415 ++input_line_pointer; 4416 regname = input_line_pointer; 4417 c = get_symbol_end (); 4418 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4419 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4420 if (regname[0] == 'i') 4421 regname = NULL; 4422 else 4423 regname = ""; 4424 } 4425 else 4426 { 4427 regname = input_line_pointer; 4428 c = get_symbol_end (); 4429 } 4430 if (sparc_arch_size == 64) 4431 { 4432 if (globals[reg]) 4433 { 4434 if ((regname && globals[reg] != (symbolS *) 1 4435 && strcmp (S_GET_NAME (globals[reg]), regname)) 4436 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4437 as_bad (_("redefinition of global register")); 4438 } 4439 else 4440 { 4441 if (regname == NULL) 4442 globals[reg] = (symbolS *) 1; 4443 else 4444 { 4445 if (*regname) 4446 { 4447 if (symbol_find (regname)) 4448 as_bad (_("Register symbol %s already defined."), 4449 regname); 4450 } 4451 globals[reg] = symbol_make (regname); 4452 flags = symbol_get_bfdsym (globals[reg])->flags; 4453 if (! *regname) 4454 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4455 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4456 flags |= BSF_GLOBAL; 4457 symbol_get_bfdsym (globals[reg])->flags = flags; 4458 S_SET_VALUE (globals[reg], (valueT) reg); 4459 S_SET_ALIGN (globals[reg], reg); 4460 S_SET_SIZE (globals[reg], 0); 4461 /* Although we actually want undefined_section here, 4462 we have to use absolute_section, because otherwise 4463 generic as code will make it a COM section. 4464 We fix this up in sparc_adjust_symtab. */ 4465 S_SET_SEGMENT (globals[reg], absolute_section); 4466 S_SET_OTHER (globals[reg], 0); 4467 elf_symbol (symbol_get_bfdsym (globals[reg])) 4468 ->internal_elf_sym.st_info = 4469 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4470 elf_symbol (symbol_get_bfdsym (globals[reg])) 4471 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4472 } 4473 } 4474 } 4475 4476 *input_line_pointer = c; 4477 4478 demand_empty_rest_of_line (); 4479 } 4480 4481 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4482 symbols which need it. */ 4483 4484 void 4485 sparc_adjust_symtab (void) 4486 { 4487 symbolS *sym; 4488 4489 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4490 { 4491 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4492 ->internal_elf_sym.st_info) != STT_REGISTER) 4493 continue; 4494 4495 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4496 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4497 continue; 4498 4499 S_SET_SEGMENT (sym, undefined_section); 4500 } 4501 } 4502 #endif 4503 4504 /* If the --enforce-aligned-data option is used, we require .word, 4505 et. al., to be aligned correctly. We do it by setting up an 4506 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4507 no unexpected alignment was introduced. 4508 4509 The SunOS and Solaris native assemblers enforce aligned data by 4510 default. We don't want to do that, because gcc can deliberately 4511 generate misaligned data if the packed attribute is used. Instead, 4512 we permit misaligned data by default, and permit the user to set an 4513 option to check for it. */ 4514 4515 void 4516 sparc_cons_align (int nbytes) 4517 { 4518 int nalign; 4519 4520 /* Only do this if we are enforcing aligned data. */ 4521 if (! enforce_aligned_data) 4522 return; 4523 4524 /* Don't align if this is an unaligned pseudo-op. */ 4525 if (sparc_no_align_cons) 4526 return; 4527 4528 nalign = mylog2 (nbytes); 4529 if (nalign == 0) 4530 return; 4531 4532 gas_assert (nalign > 0); 4533 4534 if (now_seg == absolute_section) 4535 { 4536 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4537 as_bad (_("misaligned data")); 4538 return; 4539 } 4540 4541 frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4542 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4543 4544 record_alignment (now_seg, nalign); 4545 } 4546 4547 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4548 4549 void 4550 sparc_handle_align (fragS *fragp) 4551 { 4552 int count, fix; 4553 char *p; 4554 4555 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4556 4557 switch (fragp->fr_type) 4558 { 4559 case rs_align_test: 4560 if (count != 0) 4561 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4562 break; 4563 4564 case rs_align_code: 4565 p = fragp->fr_literal + fragp->fr_fix; 4566 fix = 0; 4567 4568 if (count & 3) 4569 { 4570 fix = count & 3; 4571 memset (p, 0, fix); 4572 p += fix; 4573 count -= fix; 4574 } 4575 4576 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4577 { 4578 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4579 if (INSN_BIG_ENDIAN) 4580 number_to_chars_bigendian (p, wval, 4); 4581 else 4582 number_to_chars_littleendian (p, wval, 4); 4583 p += 4; 4584 count -= 4; 4585 fix += 4; 4586 } 4587 4588 if (INSN_BIG_ENDIAN) 4589 number_to_chars_bigendian (p, 0x01000000, 4); 4590 else 4591 number_to_chars_littleendian (p, 0x01000000, 4); 4592 4593 fragp->fr_fix += fix; 4594 fragp->fr_var = 4; 4595 break; 4596 4597 default: 4598 break; 4599 } 4600 } 4601 4602 #ifdef OBJ_ELF 4603 /* Some special processing for a Sparc ELF file. */ 4604 4605 void 4606 sparc_elf_final_processing (void) 4607 { 4608 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4609 sort of BFD interface for this. */ 4610 if (sparc_arch_size == 64) 4611 { 4612 switch (sparc_memory_model) 4613 { 4614 case MM_RMO: 4615 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4616 break; 4617 case MM_PSO: 4618 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4619 break; 4620 default: 4621 break; 4622 } 4623 } 4624 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4625 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4626 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4627 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4628 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4629 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4630 } 4631 4632 const char * 4633 sparc_cons (expressionS *exp, int size) 4634 { 4635 char *save; 4636 const char *sparc_cons_special_reloc = NULL; 4637 4638 SKIP_WHITESPACE (); 4639 save = input_line_pointer; 4640 if (input_line_pointer[0] == '%' 4641 && input_line_pointer[1] == 'r' 4642 && input_line_pointer[2] == '_') 4643 { 4644 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4645 { 4646 input_line_pointer += 7; 4647 sparc_cons_special_reloc = "disp"; 4648 } 4649 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4650 { 4651 if (size != 4 && size != 8) 4652 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4653 else 4654 { 4655 input_line_pointer += 6; 4656 sparc_cons_special_reloc = "plt"; 4657 } 4658 } 4659 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4660 { 4661 if (size != 4 && size != 8) 4662 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4663 else 4664 { 4665 input_line_pointer += 13; 4666 sparc_cons_special_reloc = "tls_dtpoff"; 4667 } 4668 } 4669 if (sparc_cons_special_reloc) 4670 { 4671 int bad = 0; 4672 4673 switch (size) 4674 { 4675 case 1: 4676 if (*input_line_pointer != '8') 4677 bad = 1; 4678 input_line_pointer--; 4679 break; 4680 case 2: 4681 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4682 bad = 1; 4683 break; 4684 case 4: 4685 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4686 bad = 1; 4687 break; 4688 case 8: 4689 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4690 bad = 1; 4691 break; 4692 default: 4693 bad = 1; 4694 break; 4695 } 4696 4697 if (bad) 4698 { 4699 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4700 sparc_cons_special_reloc, size * 8, size); 4701 } 4702 else 4703 { 4704 input_line_pointer += 2; 4705 if (*input_line_pointer != '(') 4706 { 4707 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4708 sparc_cons_special_reloc, size * 8); 4709 bad = 1; 4710 } 4711 } 4712 4713 if (bad) 4714 { 4715 input_line_pointer = save; 4716 sparc_cons_special_reloc = NULL; 4717 } 4718 else 4719 { 4720 int c; 4721 char *end = ++input_line_pointer; 4722 int npar = 0; 4723 4724 while (! is_end_of_line[(c = *end)]) 4725 { 4726 if (c == '(') 4727 npar++; 4728 else if (c == ')') 4729 { 4730 if (!npar) 4731 break; 4732 npar--; 4733 } 4734 end++; 4735 } 4736 4737 if (c != ')') 4738 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4739 sparc_cons_special_reloc, size * 8); 4740 else 4741 { 4742 *end = '\0'; 4743 expression (exp); 4744 *end = c; 4745 if (input_line_pointer != end) 4746 { 4747 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4748 sparc_cons_special_reloc, size * 8); 4749 } 4750 else 4751 { 4752 input_line_pointer++; 4753 SKIP_WHITESPACE (); 4754 c = *input_line_pointer; 4755 if (! is_end_of_line[c] && c != ',') 4756 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4757 sparc_cons_special_reloc, size * 8); 4758 } 4759 } 4760 } 4761 } 4762 } 4763 if (sparc_cons_special_reloc == NULL) 4764 expression (exp); 4765 return sparc_cons_special_reloc; 4766 } 4767 4768 #endif 4769 4770 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4771 reloc for a cons. We could use the definition there, except that 4772 we want to handle little endian relocs specially. */ 4773 4774 void 4775 cons_fix_new_sparc (fragS *frag, 4776 int where, 4777 unsigned int nbytes, 4778 expressionS *exp, 4779 const char *sparc_cons_special_reloc) 4780 { 4781 bfd_reloc_code_real_type r; 4782 4783 r = (nbytes == 1 ? BFD_RELOC_8 : 4784 (nbytes == 2 ? BFD_RELOC_16 : 4785 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4786 4787 if (target_little_endian_data 4788 && nbytes == 4 4789 && now_seg->flags & SEC_ALLOC) 4790 r = BFD_RELOC_SPARC_REV32; 4791 4792 if (sparc_cons_special_reloc) 4793 { 4794 if (*sparc_cons_special_reloc == 'd') 4795 switch (nbytes) 4796 { 4797 case 1: r = BFD_RELOC_8_PCREL; break; 4798 case 2: r = BFD_RELOC_16_PCREL; break; 4799 case 4: r = BFD_RELOC_32_PCREL; break; 4800 case 8: r = BFD_RELOC_64_PCREL; break; 4801 default: abort (); 4802 } 4803 else if (*sparc_cons_special_reloc == 'p') 4804 switch (nbytes) 4805 { 4806 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4807 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4808 } 4809 else 4810 switch (nbytes) 4811 { 4812 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4813 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4814 } 4815 } 4816 else if (sparc_no_align_cons) 4817 { 4818 switch (nbytes) 4819 { 4820 case 2: r = BFD_RELOC_SPARC_UA16; break; 4821 case 4: r = BFD_RELOC_SPARC_UA32; break; 4822 case 8: r = BFD_RELOC_SPARC_UA64; break; 4823 default: abort (); 4824 } 4825 } 4826 4827 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4828 } 4829 4830 void 4831 sparc_cfi_frame_initial_instructions (void) 4832 { 4833 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4834 } 4835 4836 int 4837 sparc_regname_to_dw2regnum (char *regname) 4838 { 4839 char *p, *q; 4840 4841 if (!regname[0]) 4842 return -1; 4843 4844 q = "goli"; 4845 p = strchr (q, regname[0]); 4846 if (p) 4847 { 4848 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4849 return -1; 4850 return (p - q) * 8 + regname[1] - '0'; 4851 } 4852 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4853 return 14; 4854 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4855 return 30; 4856 if (regname[0] == 'f' || regname[0] == 'r') 4857 { 4858 unsigned int regnum; 4859 4860 regnum = strtoul (regname + 1, &q, 10); 4861 if (p == q || *q) 4862 return -1; 4863 if (regnum >= ((regname[0] == 'f' 4864 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4865 ? 64 : 32)) 4866 return -1; 4867 if (regname[0] == 'f') 4868 { 4869 regnum += 32; 4870 if (regnum >= 64 && (regnum & 1)) 4871 return -1; 4872 } 4873 return regnum; 4874 } 4875 return -1; 4876 } 4877 4878 void 4879 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 4880 { 4881 sparc_no_align_cons = 1; 4882 emit_expr_with_reloc (exp, nbytes, "disp"); 4883 sparc_no_align_cons = 0; 4884 } 4885
