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  /art/runtime/interpreter/mterp/arm64/
header.S 74 x23 xINST first 16-bit code unit of current instruction
99 #define xINST x23
163 * src and dest registers are parameterized (not hard-wired to xPC and xINST).
171 * xINST ahead of possible exception point. Be sure to manually advance xPC
221 and \reg, xINST, #255
  /art/runtime/interpreter/mterp/out/
mterp_arm64.S 81 x23 xINST first 16-bit code unit of current instruction
106 #define xINST x23
170 * src and dest registers are parameterized (not hard-wired to xPC and xINST).
178 * xINST ahead of possible exception point. Be sure to manually advance xPC
228 and \reg, xINST, #255
331 stp xSELF, xINST, [sp, #32]
425 FETCH_ADVANCE_INST 3 // advance xPC, load xINST
427 GET_INST_OPCODE ip // extract opcode from xINST
526 FETCH_ADVANCE_INST 3 // advance xPC, load xINST
528 GET_INST_OPCODE ip // extract opcode from xINST
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