1 ; Test the MSA intrinsics that are encoded with the I8 instruction format. 2 3 ; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s 4 ; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s 5 6 @llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 7 @llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 8 9 define void @llvm_mips_andi_b_test() nounwind { 10 entry: 11 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_andi_b_ARG1 12 %1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25) 13 store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES 14 ret void 15 } 16 17 declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind 18 19 ; CHECK: llvm_mips_andi_b_test: 20 ; CHECK: ld.b 21 ; CHECK: andi.b 22 ; CHECK: st.b 23 ; CHECK: .size llvm_mips_andi_b_test 24 25 @llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 26 @llvm_mips_bmnzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 27 @llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 28 29 define void @llvm_mips_bmnzi_b_test() nounwind { 30 entry: 31 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG1 32 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmnzi_b_ARG2 33 %2 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, <16 x i8> %1, i32 25) 34 store <16 x i8> %2, <16 x i8>* @llvm_mips_bmnzi_b_RES 35 ret void 36 } 37 38 declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, <16 x i8>, i32) nounwind 39 40 ; CHECK: llvm_mips_bmnzi_b_test: 41 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG1)( 42 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmnzi_b_ARG2)( 43 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 44 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) 45 ; CHECK-DAG: bmnzi.b [[R3]], [[R4]], 25 46 ; CHECK-DAG: st.b [[R3]], 0( 47 ; CHECK: .size llvm_mips_bmnzi_b_test 48 49 @llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 50 @llvm_mips_bmzi_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 51 @llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 52 53 define void @llvm_mips_bmzi_b_test() nounwind { 54 entry: 55 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bmzi_b_ARG1 56 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bmzi_b_ARG2 57 %2 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, <16 x i8> %1, i32 25) 58 store <16 x i8> %2, <16 x i8>* @llvm_mips_bmzi_b_RES 59 ret void 60 } 61 62 declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, <16 x i8>, i32) nounwind 63 64 ; CHECK: llvm_mips_bmzi_b_test: 65 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG1)( 66 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bmzi_b_ARG2)( 67 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 68 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) 69 ; bmnzi.b is the same as bmzi.b with ws and wd_in swapped 70 ; CHECK-DAG: bmnzi.b [[R4]], [[R3]], 25 71 ; CHECK-DAG: st.b [[R4]], 0( 72 ; CHECK: .size llvm_mips_bmzi_b_test 73 74 @llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 75 @llvm_mips_bseli_b_ARG2 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 76 @llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 77 78 define void @llvm_mips_bseli_b_test() nounwind { 79 entry: 80 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_bseli_b_ARG1 81 %1 = load <16 x i8>, <16 x i8>* @llvm_mips_bseli_b_ARG2 82 %2 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %1, i32 25) 83 store <16 x i8> %2, <16 x i8>* @llvm_mips_bseli_b_RES 84 ret void 85 } 86 87 declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind 88 89 ; CHECK: llvm_mips_bseli_b_test: 90 ; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG1)( 91 ; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_bseli_b_ARG2)( 92 ; CHECK-DAG: ld.b [[R3:\$w[0-9]+]], 0([[R1]]) 93 ; CHECK-DAG: ld.b [[R4:\$w[0-9]+]], 0([[R2]]) 94 ; CHECK-DAG: bseli.b [[R3]], [[R4]], 25 95 ; CHECK-DAG: st.b [[R3]], 0( 96 ; CHECK: .size llvm_mips_bseli_b_test 97 98 @llvm_mips_nori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 99 @llvm_mips_nori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 100 101 define void @llvm_mips_nori_b_test() nounwind { 102 entry: 103 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_nori_b_ARG1 104 %1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25) 105 store <16 x i8> %1, <16 x i8>* @llvm_mips_nori_b_RES 106 ret void 107 } 108 109 declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind 110 111 ; CHECK: llvm_mips_nori_b_test: 112 ; CHECK: ld.b 113 ; CHECK: nori.b 114 ; CHECK: st.b 115 ; CHECK: .size llvm_mips_nori_b_test 116 ; 117 @llvm_mips_ori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 118 @llvm_mips_ori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 119 120 define void @llvm_mips_ori_b_test() nounwind { 121 entry: 122 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_ori_b_ARG1 123 %1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25) 124 store <16 x i8> %1, <16 x i8>* @llvm_mips_ori_b_RES 125 ret void 126 } 127 128 declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind 129 130 ; CHECK: llvm_mips_ori_b_test: 131 ; CHECK: ld.b 132 ; CHECK: ori.b 133 ; CHECK: st.b 134 ; CHECK: .size llvm_mips_ori_b_test 135 ; 136 @llvm_mips_shf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 137 @llvm_mips_shf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 138 139 define void @llvm_mips_shf_b_test() nounwind { 140 entry: 141 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_shf_b_ARG1 142 %1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25) 143 store <16 x i8> %1, <16 x i8>* @llvm_mips_shf_b_RES 144 ret void 145 } 146 147 declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind 148 149 ; CHECK: llvm_mips_shf_b_test: 150 ; CHECK: ld.b 151 ; CHECK: shf.b 152 ; CHECK: st.b 153 ; CHECK: .size llvm_mips_shf_b_test 154 ; 155 @llvm_mips_shf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16 156 @llvm_mips_shf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 157 158 define void @llvm_mips_shf_h_test() nounwind { 159 entry: 160 %0 = load <8 x i16>, <8 x i16>* @llvm_mips_shf_h_ARG1 161 %1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25) 162 store <8 x i16> %1, <8 x i16>* @llvm_mips_shf_h_RES 163 ret void 164 } 165 166 declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind 167 168 ; CHECK: llvm_mips_shf_h_test: 169 ; CHECK: ld.h 170 ; CHECK: shf.h 171 ; CHECK: st.h 172 ; CHECK: .size llvm_mips_shf_h_test 173 ; 174 @llvm_mips_shf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 175 @llvm_mips_shf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 176 177 define void @llvm_mips_shf_w_test() nounwind { 178 entry: 179 %0 = load <4 x i32>, <4 x i32>* @llvm_mips_shf_w_ARG1 180 %1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25) 181 store <4 x i32> %1, <4 x i32>* @llvm_mips_shf_w_RES 182 ret void 183 } 184 185 declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind 186 187 ; CHECK: llvm_mips_shf_w_test: 188 ; CHECK: ld.w 189 ; CHECK: shf.w 190 ; CHECK: st.w 191 ; CHECK: .size llvm_mips_shf_w_test 192 ; 193 @llvm_mips_xori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16 194 @llvm_mips_xori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 195 196 define void @llvm_mips_xori_b_test() nounwind { 197 entry: 198 %0 = load <16 x i8>, <16 x i8>* @llvm_mips_xori_b_ARG1 199 %1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25) 200 store <16 x i8> %1, <16 x i8>* @llvm_mips_xori_b_RES 201 ret void 202 } 203 204 declare <16 x i8> @llvm.mips.xori.b(<16 x i8>, i32) nounwind 205 206 ; CHECK: llvm_mips_xori_b_test: 207 ; CHECK: ld.b 208 ; CHECK: xori.b 209 ; CHECK: st.b 210 ; CHECK: .size llvm_mips_xori_b_test 211 ; 212
