| /external/libgdx/extensions/gdx-freetype/jni/freetype-2.6.2/builds/compiler/ |
| emx.mk | 64 CFLAGS ?= -c -g -O6 -Wall
|
| /external/webp/src/dsp/ |
| mips_macro.h | 51 #define MUL_SHIFT_SUM(O0, O1, O2, O3, O4, O5, O6, O7, \
60 "mul %[" #O6 "], %[" #I3 "], %[kC2] \n\t" \
68 "sra %[" #O6 "], %[" #O6 "], 16 \n\t" \
97 #define SHIFT_R_SUM_X2(O0, O1, O2, O3, O4, O5, O6, O7, \
105 "addq.ph %[" #O6 "], %[" #I3 "], %[" #I7 "] \n\t" \
113 "shra.ph %[" #O6 "], %[" #O6 "], 3 \n\t" \
141 #define CONVERT_2_BYTES_TO_HALF(O0, O1, O2, O3, O4, O5, O6, O7, \
149 "preceu.ph.qbr %[" #O6 "], %[" #I3 "] \n\t"
[all...] |
| enc_mips_dsp_r2.c | 28 #define ADD_SUB_HALVES_X4(O0, O1, O2, O3, O4, O5, O6, O7, \
36 "addq.ph %[" #O6 "], %[" #I6 "], %[" #I7 "] \n\t" \
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
53 .addReg(SP::O6).addImm(NumBytes);
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
69 .addReg(SP::O6).addReg(SP::G1);
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
82 .addReg(SP::O6).addReg(SP::G1);
180 // andn %o6, MaxAlign-1, %o6
182 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), SP::O6).addReg(SP::O6).addImm(MaxAlign - 1)
[all...] |
| SparcRegisterInfo.cpp | 71 Reserved.set(SP::O6);
|
| SparcISelLowering.cpp | 830 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
[all...] |
| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 39 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
48 unsigned Reg = MRI.getDwarfRegNum(SP::O6, true);
|
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 105 Sparc::O4, Sparc::O5, Sparc::O6, Sparc::O7,
900 RegNo = Sparc::O6;
[all...] |
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 71 SP::O4, SP::O5, SP::O6, SP::O7,
|
| /external/webrtc/talk/media/testdata/ |
| h264-svc-99-640x360.rtpdump | [all...] |
