| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.cpp | 204 SmallVector<CCValAssign, 16> ArgLocs;
205 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
208 for (auto &VA : ArgLocs) {
280 SmallVector<CCValAssign, 16> ArgLocs;
281 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
310 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
311 CCValAssign &VA = ArgLocs[i];
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 280 SmallVectorImpl<CCValAssign> &ArgLocs,
334 SmallVectorImpl<CCValAssign>::iterator B = ArgLocs.begin() + FirstVal;
437 SmallVector<CCValAssign, 16> ArgLocs;
438 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
440 AnalyzeArguments(CCInfo, ArgLocs, Ins);
448 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
449 CCValAssign &VA = ArgLocs[i];
584 SmallVector<CCValAssign, 16> ArgLocs;
585 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
587 AnalyzeArguments(CCInfo, ArgLocs, Outs)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyISelLowering.cpp | 365 SmallVector<CCValAssign, 16> ArgLocs;
366 CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
380 CCInfo.addLoc(CCValAssign::getMem(ArgLocs.size(), VT.getSimpleVT(),
403 assert(ArgLocs[ValNo].getValNo() == ValNo &&
404 "ArgLocs should remain in order and only hold varargs args");
405 unsigned Offset = ArgLocs[ValNo++].getLocMemOffset();
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 397 SmallVector<CCValAssign, 16> ArgLocs;
398 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
406 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i, ++InIdx) {
407 CCValAssign &VA = ArgLocs[i];
431 CCValAssign &NextVA = ArgLocs[++i];
603 SmallVector<CCValAssign, 16> ArgLocs;
604 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs,
611 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
612 CCValAssign &VA = ArgLocs[i];
752 SmallVector<CCValAssign, 16> ArgLocs;
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 677 SmallVector<CCValAssign, 16> ArgLocs;
678 HexagonCCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
696 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
697 CCValAssign &VA = ArgLocs[i];
719 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
720 CCValAssign &VA = ArgLocs[i];
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | [all...] |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| MipsFastISel.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/clang/lib/Sema/ |
| SemaTemplateInstantiateDecl.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | [all...] |
| SIISelLowering.cpp | 637 SmallVector<CCValAssign, 16> ArgLocs;
638 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
685 CCValAssign &VA = ArgLocs[ArgIdx++];
742 Reg = ArgLocs[ArgIdx++].getLocReg();
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FastISel.cpp | [all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
| AArch64FastISel.cpp | [all...] |
