/external/llvm/lib/Target/BPF/ |
BPFISelLowering.h | 30 BR_CC,
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BPFISelLowering.cpp | 103 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 174 case ISD::BR_CC: 488 return DAG.getNode(BPFISD::BR_CC, DL, Op.getValueType(), Chain, LHS, RHS, 520 case BPFISD::BR_CC: 521 return "BPFISD::BR_CC";
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/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.h | 58 BR_CC,
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MSP430ISelLowering.cpp | 105 setOperationAction(ISD::BR_CC, MVT::i8, Custom); 106 setOperationAction(ISD::BR_CC, MVT::i16, Custom); 193 case ISD::BR_CC: return LowerBR_CC(Op, DAG); [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 567 /// BR_CC - Conditional branch. The behavior is like that of SELECT_CC, in 571 BR_CC, [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
R600ISelLowering.cpp | 36 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 249 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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SIISelLowering.cpp | 47 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 265 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeDAG.cpp | [all...] |
SelectionDAGDumper.cpp | 282 case ISD::BR_CC: return "br_cc";
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LegalizeFloatTypes.cpp | [all...] |
LegalizeIntegerTypes.cpp | [all...] |
DAGCombiner.cpp | [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 152 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 153 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 154 setOperationAction(ISD::BR_CC, MVT::i1, Expand); 155 setOperationAction(ISD::BR_CC, MVT::i8, Expand); 156 setOperationAction(ISD::BR_CC, MVT::i16, Expand); 157 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 158 setOperationAction(ISD::BR_CC, MVT::i64, Expand); [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | [all...] |
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyISelLowering.cpp | 173 for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
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/external/llvm/lib/Target/Mips/ |
MipsISelLowering.cpp | 324 setOperationAction(ISD::BR_CC, MVT::f32, Expand); 325 setOperationAction(ISD::BR_CC, MVT::f64, Expand); 326 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 327 setOperationAction(ISD::BR_CC, MVT::i64, Expand); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 119 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 120 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 121 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 122 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 166 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 276 setOperationAction(ISD::BR_CC, MVT::f16, Promote); 346 setOperationAction(ISD::BR_CC, MVT::v4f16, Expand); 379 setOperationAction(ISD::BR_CC, MVT::v8f16, Expand); 551 setOperationAction(ISD::BR_CC, MVT::v1f64, Expand); [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | 70 setOperationAction(ISD::BR_CC, MVT::i32, Expand); 71 setOperationAction(ISD::BR_CC, MVT::f32, Expand); [all...] |
AMDGPUISelLowering.cpp | 205 setOperationAction(ISD::BR_CC, MVT::i1, Expand); [all...] |
/external/llvm/lib/Target/XCore/ |
XCoreISelLowering.cpp | 91 setOperationAction(ISD::BR_CC, MVT::i32, Expand); [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | 296 setOperationAction(ISD::BR_CC , MVT::f32, Expand); 297 setOperationAction(ISD::BR_CC , MVT::f64, Expand); 298 setOperationAction(ISD::BR_CC , MVT::f80, Expand); 299 setOperationAction(ISD::BR_CC , MVT::f128, Expand); 300 setOperationAction(ISD::BR_CC , MVT::i8, Expand); 301 setOperationAction(ISD::BR_CC , MVT::i16, Expand); 302 setOperationAction(ISD::BR_CC , MVT::i32, Expand); 303 setOperationAction(ISD::BR_CC , MVT::i64, Expand); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 143 // Lower SELECT_CC and BR_CC into separate comparisons and branches. 145 setOperationAction(ISD::BR_CC, VT, Custom); 153 // Expand BRCOND into a BR_CC (see above). [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | [all...] |