/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorTypes.cpp | 446 case ISD::CONCAT_VECTORS: 599 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; 805 assert(!(N->getNumOperands() & 1) && "Unsupported CONCAT_VECTORS"); 818 Lo = DAG.getNode(ISD::CONCAT_VECTORS, dl, LoVT, LoOps); 821 Hi = DAG.getNode(ISD::CONCAT_VECTORS, dl, HiVT, HiOps); [all...] |
DAGCombiner.cpp | [all...] |
SelectionDAGDumper.cpp | 219 case ISD::CONCAT_VECTORS: return "concat_vectors";
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LegalizeIntegerTypes.cpp | 102 case ISD::CONCAT_VECTORS: 719 return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2); [all...] |
SelectionDAGBuilder.cpp | 299 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 301 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS 527 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); [all...] |
LegalizeDAG.cpp | [all...] |
SelectionDAG.cpp | [all...] |
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 279 /// CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of 283 CONCAT_VECTORS, [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
X86IntrinsicsInfo.h | 344 X86_INTRINSIC_DATA(avx512_kunpck_bw, KUNPCK, ISD::CONCAT_VECTORS, 0), 345 X86_INTRINSIC_DATA(avx512_kunpck_dq, KUNPCK, ISD::CONCAT_VECTORS, 0), 346 X86_INTRINSIC_DATA(avx512_kunpck_wd, KUNPCK, ISD::CONCAT_VECTORS, 0), [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 171 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom); 173 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 174 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 619 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); [all...] |
SIISelLowering.cpp | 218 case ISD::CONCAT_VECTORS: [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 494 setTargetDAGCombine(ISD::CONCAT_VECTORS); 673 setOperationAction(ISD::CONCAT_VECTORS, VT.getSimpleVT(), Legal); [all...] |
/external/llvm/lib/Target/ARM/ |
ARMISelLowering.cpp | 116 setOperationAction(ISD::CONCAT_VECTORS, VT, Legal); [all...] |
ARMISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | 787 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand); [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 680 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand); 730 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand); [all...] |