| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arm6.s | 4 mrs r8, cpsr
7 msr cpsr, r1
12 mrs r8, CPSR
15 msr CPSR, r1
|
| mrs-msr-arm-v6.d | 8 0+00 <[^>]*> e10f4000 mrs r4, CPSR
9 0+04 <[^>]*> e10f5000 mrs r5, CPSR
|
| mrs-msr-arm-v7-a.d | 8 0+00 <[^>]*> e10f4000 mrs r4, CPSR
9 0+04 <[^>]*> e10f5000 mrs r5, CPSR
|
| mrs-msr-thumb-v6t2.d | 10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
11 0+04 <[^>]*> f3ef 8500 mrs r5, CPSR
|
| arm6.d | 8 0+00 <[^>]+> e10f8000 ? mrs r8, CPSR
14 0+18 <[^>]+> e10f8000 ? mrs r8, CPSR
|
| mrs-msr-thumb-v7-m.d | 10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
|
| mrs-msr-thumb-v7e-m.d | 10 0+00 <[^>]*> f3ef 8400 mrs r4, CPSR
|
| thumb-w-good.d | 9 00000004 <.text\+0x4> f3ef 8000 mrs r0, CPSR
|
| msr-imm.s | 14 @ Write to CPSR flags
15 msr CPSR,#0xc0000004
21 @ Write to CPSR flag combos
|
| msr-reg.s | 13 @ Write to CPSR flags
14 msr CPSR,r9
20 @ Write to CPSR flag combos
|
| arch7.d | 50 0+0a0 <[^>]*> f3ef 8000 mrs r0, (CPSR|APSR)
|
| /external/v8/src/arm/ |
| constants-arm.h | 234 CPSR = 0 << 22,
257 CPSR_c = CPSR | 1 << 16,
258 CPSR_x = CPSR | 1 << 17,
259 CPSR_s = CPSR | 1 << 18,
260 CPSR_f = CPSR | 1 << 19,
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2SizeReduction.cpp | 54 // 2 - Always set CPSR.
188 // Last instruction to define CPSR in the current block.
190 // Was CPSR last defined by a high latency instruction?
191 // When CPSRDef is null, this refers to CPSR defs in predecessors.
222 if (*Regs == ARM::CPSR)
238 /// the 's' 16-bit instruction partially update CPSR. Abort the
239 /// transformation to avoid adding false dependency on last CPSR setting
243 /// last instruction that defines the CPSR and the current instruction. If there
245 /// before the CPSR setting instruction anyway.
270 if (Reg == 0 || Reg == ARM::CPSR)
[all...] |
| Thumb2ITBlockPass.cpp | 88 if (Reg == ARM::CPSR)
139 // If the CPSR is defined by this copy, then we don't want to move it. E.g.,
157 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
|
| ARMMCInstLower.cpp | 73 // Ignore all non-CPSR implicit register operands.
74 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
|
| ARMBaseInstrInfo.cpp | 410 // For conditional branches, we use addOperand to preserve CPSR flags.
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
521 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
585 if (MO.getReg() != ARM::CPSR)
590 // all definitions of CPSR are dead
677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
699 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
789 } else if (SrcReg == ARM::CPSR) {
792 } else if (DestReg == ARM::CPSR) {
[all...] |
| ARMFastISel.cpp | 214 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
227 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR.
228 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) {
232 // Look to see if our OptionalDef is defining CPSR or CCR.
236 if (MO.getReg() == ARM::CPSR)
237 *CPSR = true;
260 // CPSR defs that need to be added before the remaining operands. See s_cc_out
273 // defines CPSR. All other OptionalDefines in ARM are the CCR register.
274 bool CPSR = false
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/arm/ |
| list5.go | 66 return "CPSR"
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/arm/ |
| list5.go | 66 return "CPSR"
|
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm/ |
| list5.go | 69 return "CPSR"
|
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm/ |
| list5.go | 69 return "CPSR"
|
| /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/arm/armasm/ |
| objdump_test.go | 87 // word 510F4000. we say apsr, libopcodes says CPSR.
88 if strings.Replace(dec.text, "CPSR", "apsr", -1) == text {
|
| /prebuilts/go/linux-x86/src/cmd/internal/rsc.io/arm/armasm/ |
| objdump_test.go | 87 // word 510F4000. we say apsr, libopcodes says CPSR.
88 if strings.Replace(dec.text, "CPSR", "apsr", -1) == text {
|
| /prebuilts/go/darwin-x86/src/runtime/ |
| softfloat_arm.go | 63 // conditions array record the required CPSR cond field for the
80 var i, opc, regd, regm, regn, cpsr uint32
88 print("stepflt ", pc, " ", hex(i), " (cpsr ", hex(regs[_CPSR]>>28), ")\n")
96 cpsr = regs[_CPSR] >> 28
99 if cpsr&(conditions[opc/2]>>4) == conditions[opc/2]>>4 &&
100 cpsr&(conditions[opc/2]&0xf) == 0 {
111 if cpsr&(_FLAGS_N>>28) == cpsr&(_FLAGS_V>>28) {
122 if cpsr&(_FLAGS_N>>28) == cpsr&(_FLAGS_V>>28) &
[all...] |
| /prebuilts/go/linux-x86/src/runtime/ |
| softfloat_arm.go | 63 // conditions array record the required CPSR cond field for the
80 var i, opc, regd, regm, regn, cpsr uint32
88 print("stepflt ", pc, " ", hex(i), " (cpsr ", hex(regs[_CPSR]>>28), ")\n")
96 cpsr = regs[_CPSR] >> 28
99 if cpsr&(conditions[opc/2]>>4) == conditions[opc/2]>>4 &&
100 cpsr&(conditions[opc/2]&0xf) == 0 {
111 if cpsr&(_FLAGS_N>>28) == cpsr&(_FLAGS_V>>28) {
122 if cpsr&(_FLAGS_N>>28) == cpsr&(_FLAGS_V>>28) &
[all...] |
