/device/google/contexthub/firmware/src/platform/stm32f4xx/ |
crc.c | 25 volatile uint32_t DR; 61 if (mCrcRegs->DR == crc) 66 mCrcRegs->DR = revCrc32Word(crc, mCrcRegs->DR, 8); 69 mCrcRegs->DR = words[i]; 77 mCrcRegs->DR = word; 80 crc = mCrcRegs->DR;
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/toolchain/binutils/binutils-2.25/opcodes/ |
rx-decode.opc | 107 #define DR(r) OP (0, RX_Operand_Register, r, 0) 285 ID(mov); DR(rdst); SC(IMM (1)); F_____; 304 ID(mov); DR(rdst); SC(immm); F_____; 329 ID(mov); sBWL(sz); DR(dst); SIs(src, dsp*4+a*2+b, sz); F_____; 335 ID(movbi); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; 338 ID(movbir); sBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; 341 ID(movbi); uBWL(sz); DR(rdst); SRR(isrc); S2R(bsrc); F_____; 348 ID(mov); sBWL (sz); DR(rdst); F_____; 352 ID(mov); uBWL(w); DR(dst); SIs(src, dsp*4+a*2+b, w); F_____; 355 ID(mov); uBWL(s); SD(ss, rsrc, s); DR(rdst); F_____ [all...] |
rl78-decode.opc | 108 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0) 115 #define DCY() DR(PSW); DB(0) 200 ID(add); DR(A); SM(None, IMMU(2)); Fzac; 203 ID(add); DR(A); SM(HL, 0); Fzac; 206 ID(add); DR(A); SM2(HL, B, 0); Fzac; 209 ID(add); DR(A); SM(HL, IMMU(1)); Fzac; 212 ID(add); DR(A); SM2(HL, C, 0); Fzac; 215 ID(add); DR(A); SC(IMMU(1)); Fzac; 218 ID(add); DR(A); SRB(rba); Fzac; 221 ID(add); DR(A); SM(None, SADDR); Fzac [all...] |
m32r-opc.c | 222 /* add $dr,$sr */ 225 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 228 /* add3 $dr,$sr,$hash$slo16 */ 231 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (HASH), OP (SLO16), 0 } }, 234 /* and $dr,$sr */ 237 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } }, 240 /* and3 $dr,$sr,$uimm16 */ 243 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 } }, 246 /* or $dr,$sr */ 249 { { MNEM, ' ', OP (DR), ',', OP (SR), 0 } } [all...] |
msp430-decode.opc | 79 #define DR(r) OP (0, MSP430_Operand_Register, r, 0) 186 DR (reg); 438 ID (MSO_mov); SM (srcr, 0); DR (dstr); 443 ID (MSO_mov); SI (srcr); DR (dstr); 448 ID (MSO_mov); SA ((srcr << 16) + IMMU(2)); DR (dstr); 453 ID (MSO_mov); SM (srcr, IMMS(2)); DR (dstr); 468 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr); 473 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr); 479 ID (MSO_add); SC ((srcr << 16) + IMMU(2)); DR (dstr); 485 ID (MSO_sub); SC ((srcr << 16) + IMMU(2)); DR (dstr) [all...] |
rl78-decode.c | 109 #define DR(r) OP (0, RL78_Operand_Register, RL78_Reg_##r, 0) 116 #define DCY() DR(PSW); DB(0) 227 ID(add); W(); DR(AX); SRW(rw); Fzac; 242 ID(add); W(); DR(AX); SM(None, IMMU(2)); Fzac; 257 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac; 272 ID(add); W(); DR(AX); SM(None, SADDR); Fzac; 287 ID(xch); DR(A); SR(X); 304 ID(mov); DR(A); SM(B, IMMU(2)); 336 ID(add); DR(A); SM(None, SADDR); Fzac; 351 ID(add); DR(A); SC(IMMU(1)); Fzac [all...] |
m32r-opinst.c | 45 { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 47 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 54 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 61 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 }, 68 { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 } [all...] |
xc16x-opc.c | 482 /* add $dr,$hash$pof$uimm3 */ 485 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, 488 /* sub $dr,$hash$pof$uimm3 */ 491 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } }, 506 /* add $dr,$hash$pag$uimm3 */ 509 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, 512 /* sub $dr,$hash$pag$uimm3 */ 515 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (PAG), OP (UIMM3), 0 } }, 578 /* addc $dr,$hash$pof$uimm3 */ 581 { { MNEM, ' ', OP (DR), ',', OP (HASH), OP (POF), OP (UIMM3), 0 } } [all...] |
/external/pcre/dist/sljit/ |
sljitNativeSPARC_32.c | 30 return push_inst(compiler, OR | D(dst) | S1(0) | IMM(imm), DR(dst)); 32 FAIL_IF(push_inst(compiler, SETHI | D(dst) | ((imm >> 10) & 0x3fffff), DR(dst))); 33 return (imm & 0x3ff) ? push_inst(compiler, OR | D(dst) | S1(dst) | IMM_ARG | (imm & 0x3ff), DR(dst)) : SLJIT_SUCCESS; 50 return push_inst(compiler, OR | D(dst) | S1(0) | S2(src2), DR(dst)); 58 return push_inst(compiler, AND | D(dst) | S1(src2) | IMM(0xff), DR(dst)); 59 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst))); 60 return push_inst(compiler, SRA | D(dst) | S1(dst) | IMM(24), DR(dst)); 70 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst))); 71 return push_inst(compiler, (op == SLJIT_MOV_SH ? SRA : SRL) | D(dst) | S1(dst) | IMM(16), DR(dst)); 79 return push_inst(compiler, XNOR | (flags & SET_FLAGS) | D(dst) | S1(0) | S2(src2), DR(dst) | (flags & SET_FLAGS)) [all...] |
sljitNativeMIPS_64.c | 129 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \ 135 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \ 150 FAIL_IF(push_inst(compiler, ins | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \ 157 FAIL_IF(push_inst(compiler, ins | S(src2) | T(src1) | D(dst), DR(dst))); \ 170 return push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src2) | TA(0) | D(dst), DR(dst)); 178 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(24), DR(dst))); 179 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(24), DR(dst)); 181 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); 192 FAIL_IF(push_inst(compiler, DSLL32 | T(src2) | D(dst) | SH_IMM(16), DR(dst))); 193 return push_inst(compiler, DSRA32 | T(dst) | D(dst) | SH_IMM(16), DR(dst)) [all...] |
sljitNativeMIPS_32.c | 46 FAIL_IF(push_inst(compiler, op_imm | S(src1) | T(dst) | IMM(src2), DR(dst))); \ 52 FAIL_IF(push_inst(compiler, op_norm | S(src1) | T(src2) | D(dst), DR(dst))); \ 60 FAIL_IF(push_inst(compiler, op_imm | T(src1) | D(dst) | SH_IMM(src2), DR(dst))); \ 66 FAIL_IF(push_inst(compiler, op_v | S(src2) | T(src1) | D(dst), DR(dst))); \ 79 return push_inst(compiler, ADDU | S(src2) | TA(0) | D(dst), DR(dst)); 88 return push_inst(compiler, SEB | T(src2) | D(dst), DR(dst)); 90 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(24), DR(dst))); 91 return push_inst(compiler, SRA | T(dst) | D(dst) | SH_IMM(24), DR(dst)); 94 return push_inst(compiler, ANDI | S(src2) | T(dst) | IMM(0xff), DR(dst)); 106 return push_inst(compiler, SEH | T(src2) | D(dst), DR(dst)) [all...] |
sljitNativeMIPS_common.c | 92 #define DR(dr) (reg_map[dr]) 562 FAIL_IF(push_inst(compiler, ADDIU_W | S(SLJIT_SP) | T(SLJIT_SP) | IMM(-local_size), DR(SLJIT_SP))); 566 FAIL_IF(load_immediate(compiler, DR(TMP_REG1), local_size)); 567 FAIL_IF(push_inst(compiler, ADDU_W | S(SLJIT_SP) | TA(0) | D(TMP_REG2), DR(TMP_REG2))); 568 FAIL_IF(push_inst(compiler, SUBU_W | S(SLJIT_SP) | T(TMP_REG1) | D(SLJIT_SP), DR(SLJIT_SP))); 588 FAIL_IF(push_inst(compiler, ADDU_W | SA(4) | TA(0) | D(SLJIT_S0), DR(SLJIT_S0))); 590 FAIL_IF(push_inst(compiler, ADDU_W | SA(5) | TA(0) | D(SLJIT_S1), DR(SLJIT_S1))); 592 FAIL_IF(push_inst(compiler, ADDU_W | SA(6) | TA(0) | D(SLJIT_S2), DR(SLJIT_S2))) [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
CheckerHelpers.cpp | 35 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S); 37 if (DR && isa<EnumConstantDecl>(DR->getDecl())) 49 const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(S); 51 if (DR) 52 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl()))
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/toolchain/binutils/binutils-2.25/ld/testsuite/ld-frv/ |
fdpic-pie-5.d | 3 #objdump: -DR -j .text -j .data -j .got -j .plt
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fdpic-pie-6-fail.d | 3 #objdump: -DR -j .text -j .data -j .got -j .plt
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fdpic-shared-6-fail.d | 3 #objdump: -DR -j .text -j .data -j .got -j .plt
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fdpic-shared-8-fail.d | 3 #objdump: -DR -j .text -j .data -j .got -j .plt
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tls-dynamic-3.d | 3 #objdump: -DR -j .text -j .got -j .plt
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tls-pie-3.d | 3 #objdump: -DR -j .text -j .got -j .plt
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tls-relax-dynamic-3.d | 3 #objdump: -DR -j .text -j .got -j .plt
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/external/clang/lib/StaticAnalyzer/Checkers/ |
DeadStoresChecker.cpp | 54 bool VisitDeclRefExpr(DeclRefExpr *DR) { 56 if (const VarDecl *D = dyn_cast<VarDecl>(DR->getDecl())) 229 void CheckDeclRef(const DeclRefExpr *DR, const Expr *Val, DeadStoreKind dsk, 231 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) 232 CheckVarDecl(VD, DR, Val, dsk, Live); 245 const DeclRefExpr *DR; 247 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getLHS()->IgnoreParenCasts()))) 248 if (DR->getDecl() == VD) 251 if ((DR = dyn_cast<DeclRefExpr>(BRHS->getRHS()->IgnoreParenCasts()))) 252 if (DR->getDecl() == VD [all...] |
MallocOverflowSecurityChecker.cpp | 144 const Decl *getDecl(const DeclRefExpr *DR) { return DR->getDecl(); } 149 void Erase(const T1 *DR, std::function<bool(theVecType::iterator)> pred) { 155 if ((getDecl(DR_i) == getDecl(DR)) && pred(i)) 164 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) 165 Erase<DeclRefExpr>(DR, PredTrue); 218 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) 219 Erase<DeclRefExpr>(DR, pred);
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/external/llvm/lib/Target/Hexagon/ |
HexagonGenMux.cpp | 72 MuxInfo(MachineBasicBlock::iterator It, unsigned DR, unsigned PR, 75 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(D1), 205 unsigned DR = MI->getOperand(0).getReg(); 206 if (isRegPair(DR)) 211 CondsetMap::iterator F = CM.find(DR); 221 auto It = CM.insert(std::make_pair(DR, CondsetInfo())); 233 // There is now a complete definition of DR, i.e. we have the predicate 268 if (DU.Defs[PR] || DU.Defs[DR] || DU.Uses[DR]) { 285 ML.push_back(MuxInfo(At, DR, PR, SrcT, SrcF, Def1, Def2)) [all...] |
/external/clang/lib/Analysis/ |
LiveVariables.cpp | 208 void VisitDeclRefExpr(DeclRefExpr *DR); 340 if (DeclRefExpr *DR = dyn_cast<DeclRefExpr>(LHS)) 341 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) { 352 observer->observerKill(DR); 366 void TransferFunctions::VisitDeclRefExpr(DeclRefExpr *DR) { 367 if (const VarDecl *D = dyn_cast<VarDecl>(DR->getDecl())) 368 if (!isAlwaysAlive(D) && LV.inAssignment.find(DR) == LV.inAssignment.end()) 382 DeclRefExpr *DR = nullptr; 389 else if ((DR = dyn_cast<DeclRefExpr>(cast<Expr>(element)->IgnoreParens()))) { 390 VD = cast<VarDecl>(DR->getDecl()) [all...] |
PseudoConstantAnalysis.cpp | 70 if (const DeclRefExpr *DR = dyn_cast<DeclRefExpr>(E)) 71 return DR->getDecl(); 201 const DeclRefExpr *DR = cast<DeclRefExpr>(Head); 202 if (const VarDecl *VD = dyn_cast<VarDecl>(DR->getDecl())) {
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