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  /external/llvm/lib/Transforms/InstCombine/
InstCombineSimplifyDemanded.cpp 27 /// are any bits set in the constant that are not demanded. If so, shrink the
30 APInt Demanded) {
38 // If there are no bits set that aren't demanded, nothing to do.
39 Demanded = Demanded.zextOrTrunc(OpC->getValue().getBitWidth());
40 if ((~Demanded & OpC->getValue()) == 0)
43 // This instruction is producing bits that are not demanded. Shrink the RHS.
44 Demanded &= OpC->getValue();
45 I->setOperand(OpNo, ConstantInt::get(OpC->getType(), Demanded));
84 /// value based on the demanded bits. When this function is called, it is know
    [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
TargetLowering.cpp 295 /// are any bits set in the constant that are not demanded. If so, shrink the
298 const APInt &Demanded) {
311 (C->getAPIntValue() | (~Demanded)).isAllOnesValue())
315 if (C->getAPIntValue().intersects(~Demanded)) {
318 DAG.getConstant(Demanded &
338 const APInt &Demanded,
357 unsigned DemandedSize = BitWidth - Demanded.countLeadingZeros();
457 // If all of the demanded bits are known one on one side, return the other.
463 // If all of the demanded bits in the inputs are known zeros, return zero.
488 // If all of the demanded bits are known zero on one side, return the other
    [all...]
DAGCombiner.cpp 184 APInt Demanded = APInt::getAllOnesValue(BitWidth);
185 return SimplifyDemandedBits(Op, Demanded);
188 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded);
    [all...]
  /external/llvm/include/llvm/Target/
TargetLowering.h     [all...]
  /external/llvm/lib/Target/AMDGPU/
AMDGPUISelLowering.cpp     [all...]
SIISelLowering.cpp     [all...]

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