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  /toolchain/binutils/binutils-2.25/include/opcode/
i960.h 117 #define FL2 OP( 1, LIT, FP, 0 )
354 { R_3(0x676), "scalerl", I_FP, REG, 3, { RL, FL2,F2 } },
370 { R_3(0x690), "atanrl", I_FP, REG, 3, { FL2,FL2,F2 } },
371 { R_3(0x691), "logeprl", I_FP, REG, 3, { FL2,FL2,F2 } },
372 { R_3(0x692), "logrl", I_FP, REG, 3, { FL2,FL2,F2 } },
373 { R_3(0x693), "remrl", I_FP, REG, 3, { FL2,FL2,F2 } }
    [all...]
  /toolchain/binutils/binutils-2.25/opcodes/
ppc-opc.c 338 /* The FL2 field in a POWER SC form instruction. */
339 #define FL2 FL1 + 1
343 #define FLM FL2 + 1
    [all...]

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