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    Searched refs:FLD_Rn (Results 1 - 5 of 5) sorted by null

  /toolchain/binutils/binutils-2.25/opcodes/
aarch64-opc-2.c 29 {AARCH64_OPND_CLASS_INT_REG, "Rn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register"},
37 {AARCH64_OPND_CLASS_INT_REG, "Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer or stack pointer register"},
42 {AARCH64_OPND_CLASS_FP_REG, "Fn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a floating-point register"},
48 {AARCH64_OPND_CLASS_SISD_REG, "Sn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD scalar register"},
51 {AARCH64_OPND_CLASS_SIMD_REG, "Vn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register"},
54 {AARCH64_OPND_CLASS_FP_REG, "VnD1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "the top half of a 128-bit FP/SIMD register"},
56 {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
58 {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"},
103 {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
aarch64-asm.c 496 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
511 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
543 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
589 insert_field (FLD_Rn, code, info->addr.base_regno, 0);
    [all...]
aarch64-opc.h 45 FLD_Rn,
aarch64-dis.c 833 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
847 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
890 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
944 info->addr.base_regno = extract_field (FLD_Rn, code, 0);
    [all...]
aarch64-tbl.h     [all...]

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