/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 448 /// X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type 451 /// normal rounding, if it is 1, this FP_ROUND is known to not change the 457 /// FP_EXTEND(FP_ROUND(X,1)) -> X which are not safe for 458 /// FP_EXTEND(FP_ROUND(X,0)) because the extra bits aren't removed. 459 FP_ROUND, [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
LegalizeVectorTypes.cpp | 56 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; 202 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), 458 case ISD::FP_ROUND: 557 SDValue Res = DAG.getNode(ISD::FP_ROUND, SDLoc(N), 644 case ISD::FP_ROUND: [all...] |
LegalizeFloatTypes.cpp | 95 case ISD::FP_ROUND: R = SoftenFloatRes_FP_ROUND(N); break; 490 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); [all...] |
LegalizeVectorOps.cpp | 323 case ISD::FP_ROUND: 427 return DAG.getNode(ISD::FP_ROUND, dl, VT, Op, DAG.getIntPtrConstant(0, dl)); [all...] |
LegalizeDAG.cpp | [all...] |
SelectionDAGDumper.cpp | 248 case ISD::FP_ROUND: return "fp_round";
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DAGCombiner.cpp | 623 case ISD::FP_ROUND: 703 case ISD::FP_ROUND: 704 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), [all...] |
SelectionDAG.cpp | [all...] |
SelectionDAGBuilder.cpp | 223 // FP_ROUND's are always exact here. 226 ISD::FP_ROUND, DL, ValueVT, Val, [all...] |
/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 57 { ISD::FP_ROUND, MVT::v2f64, 2 }, 62 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND ||
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ARMISelLowering.cpp | 574 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); 681 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); [all...] |
/external/llvm/lib/Target/X86/ |
X86TargetTransformInfo.cpp | 553 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 1 }, 636 { ISD::FP_ROUND, MVT::v8f32, MVT::v8f64, 3 }, [all...] |
X86ISelDAGToDAG.cpp | 592 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) 624 if (N->getOpcode() == ISD::FP_ROUND) 625 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 641 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the [all...] |
X86IntrinsicsInfo.h | 525 ISD::FP_ROUND, 0), 527 ISD::FP_ROUND, X86ISD::VFPROUND), [all...] |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 185 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); 186 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); 317 setOperationAction(ISD::FP_ROUND, MVT::v4f16, Promote); 323 AddPromotedToType(ISD::FP_ROUND, MVT::v4f16, MVT::v4f32); 560 setOperationAction(ISD::FP_ROUND, MVT::v1f64, Expand); [all...] |
/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/ |
R600ISelLowering.cpp | 168 setTargetDAGCombine(ISD::FP_ROUND); [all...] |
SIISelLowering.cpp | 201 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand); [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCISelLowering.cpp | 133 // from FP_ROUND: that rounds to nearest, this rounds to zero. 689 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal); [all...] |
/external/llvm/lib/Target/SystemZ/ |
SystemZISelLowering.cpp | 439 setTargetDAGCombine(ISD::FP_ROUND); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |