| /external/valgrind/VEX/priv/ |
| guest_arm_toIR.c | 156 /* MOD. Initially IRTemp_INVALID. If the r15 branch to be generated
159 IRTemp_INVALID. */
336 if (guardT == IRTemp_INVALID) {
349 if (guardT == IRTemp_INVALID) {
578 register: if guardT == IRTemp_INVALID then the write is
594 if (guardT == IRTemp_INVALID) {
607 vassert(r15guard == IRTemp_INVALID);
618 if guardT == IRTemp_INVALID then the write is unconditional. */
627 if (guardT == IRTemp_INVALID) {
714 register: if guardT == IRTemp_INVALID then the write i
[all...] |
| guest_amd64_toIR.c | [all...] |
| guest_arm64_toIR.c | 313 //ZZ if (guardT == IRTemp_INVALID) {
326 //ZZ if (guardT == IRTemp_INVALID) {
371 vassert(t1 && *t1 == IRTemp_INVALID);
372 vassert(t2 && *t2 == IRTemp_INVALID);
380 vassert(t1 && *t1 == IRTemp_INVALID);
381 vassert(t2 && *t2 == IRTemp_INVALID);
382 vassert(t3 && *t3 == IRTemp_INVALID);
391 vassert(t1 && *t1 == IRTemp_INVALID);
392 vassert(t2 && *t2 == IRTemp_INVALID);
393 vassert(t3 && *t3 == IRTemp_INVALID);
[all...] |
| guest_tilegx_toIR.c | 783 stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t2, Iend_LE,
797 stmt( IRStmt_CAS(mkIRCAS(IRTemp_INVALID, t3, Iend_LE,
928 mkIRCAS(IRTemp_INVALID,
942 mkIRCAS(IRTemp_INVALID,
974 mkIRCAS(IRTemp_INVALID,
989 mkIRCAS(IRTemp_INVALID,
1006 mkIRCAS(IRTemp_INVALID,
1021 mkIRCAS(IRTemp_INVALID,
1037 mkIRCAS(IRTemp_INVALID,
1057 mkIRCAS(IRTemp_INVALID,
[all...] |
| guest_x86_toIR.c | 762 cas = mkIRCAS( IRTemp_INVALID, oldTmp, Iend_LE, addr,
[all...] |
| guest_ppc_toIR.c | 698 vassert(vEvn && *vEvn == IRTemp_INVALID);
699 vassert(vOdd && *vOdd == IRTemp_INVALID);
716 vassert(vEvn && *vEvn == IRTemp_INVALID);
717 vassert(vOdd && *vOdd == IRTemp_INVALID);
734 vassert(vEvn && *vEvn == IRTemp_INVALID);
735 vassert(vOdd && *vOdd == IRTemp_INVALID);
752 vassert(vEvn && *vEvn == IRTemp_INVALID);
753 vassert(vOdd && *vOdd == IRTemp_INVALID);
773 vassert(t0 && *t0 == IRTemp_INVALID);
774 vassert(t1 && *t1 == IRTemp_INVALID);
[all...] |
| ir_defs.c | 114 if (tmp == IRTemp_INVALID)
115 vex_printf("IRTemp_INVALID");
[all...] |
| host_mips_isel.c | [all...] |
| host_x86_isel.c | [all...] |
| host_tilegx_isel.c | [all...] |
| host_s390_isel.c | [all...] |
| host_amd64_isel.c | [all...] |
| ir_opt.c | [all...] |
| host_arm64_isel.c | [all...] |
| guest_s390_toIR.c | [all...] |
| host_ppc_isel.c | [all...] |
| guest_mips_toIR.c | [all...] |
| host_arm_isel.c | [all...] |
| /external/valgrind/exp-sgcheck/ |
| h_main.c | 485 IRTemp_INVALID if code to compute the shadow has not yet been
489 IRTemp_INVALID, since it is illogical for a shadow tmp itself to be
566 IRTemp_INVALID and we are hoping to read that shadow tmp, it means
581 ent.shadow = IRTemp_INVALID;
651 ent.shadow = IRTemp_INVALID;
|
| /external/valgrind/coregrind/ |
| m_translate.c | 136 // - Unused slots have a .temp value of 'IRTemp_INVALID'.
139 // non-IRTemp_INVALID values. This is rare, and the overwriting of a
141 // - Every slot below next_SP_alias_slot holds a non-IRTemp_INVALID value.
162 SP_aliases[i].temp = IRTemp_INVALID;
170 vg_assert(temp != IRTemp_INVALID);
180 vg_assert(IRTemp_INVALID != temp);
202 if (SP_aliases[i].temp == IRTemp_INVALID) {
[all...] |
| /external/valgrind/memcheck/ |
| mc_translate.c | 157 and origin (shadowB) values, or these may be IRTemp_INVALID if code
161 and so .shadowV and .shadowB must be IRTemp_INVALID, since it is
241 IRTemp_INVALID and we are hoping to read that shadow tmp, it means
256 ent.shadowV = IRTemp_INVALID;
257 ent.shadowB = IRTemp_INVALID;
273 if (ent->shadowV == IRTemp_INVALID) {
280 tl_assert(ent->shadowV == IRTemp_INVALID);
[all...] |
| /external/valgrind/VEX/useful/ |
| test_main.c | 565 Initially all entries are IRTemp_INVALID. Entries are added
613 if (mce->tmpMap[orig] == IRTemp_INVALID) {
[all...] |
| /external/valgrind/VEX/pub/ |
| libvex_ir.h | 400 #define IRTemp_INVALID ((IRTemp)0xFFFFFFFF)
[all...] |
| /external/valgrind/helgrind/ |
| hg_main.c | [all...] |
