/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCInstrInfo.h | 56 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, 66 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 71 void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI); 77 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB, 83 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst, 93 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII, 97 unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI); 100 unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI); 102 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI); 108 SmallVector<DuplexCandidate, 8> getDuplexPossibilties(MCInstrInfo const &MCII, [all...] |
HexagonMCShuffler.h | 30 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 32 : HexagonShuffler(MCII, STI) { 35 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 38 : HexagonShuffler(MCII, STI) { 56 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 58 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 60 unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
|
HexagonMCInstrInfo.cpp | 32 MCInstrInfo const &MCII, MCInst &MCB, 36 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); 40 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); 58 bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, 65 HexagonMCInstrInfo::tryCompound(MCII, Context, MCB); 70 HexagonMCShuffle(MCII, STI, MCB); 76 possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB); 77 HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes); 86 HexagonMCShuffle(MCII, STI, MCB); 90 void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, [all...] |
HexagonMCChecker.cpp | 58 const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); 67 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { 70 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); 73 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) 109 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) 145 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && isPredicateRegister(*SRI)) 148 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD) 153 else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD) 160 else if (i <= 1 && llvm::HexagonMCInstrInfo::hasNewValue2(MCII, MCI) ) 170 if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) [all...] |
HexagonShuffler.cpp | 130 HexagonCVIResource::HexagonCVIResource(MCInstrInfo const &MCII, unsigned s, 133 unsigned T = HexagonMCInstrInfo::getType(MCII, *id); 140 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); 141 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); 152 HexagonShuffler::HexagonShuffler(MCInstrInfo const &MCII, 154 : MCII(MCII), STI(STI) { 166 HexagonInstr PI(MCII, ID, Extender, S, X); 204 if (HexagonMCInstrInfo::isSolo(MCII, *ID)) 206 else if (HexagonMCInstrInfo::isSoloAX(MCII, *ID) [all...] |
HexagonMCCodeEmitter.cpp | 37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)), 43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); 107 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() && 110 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" 113 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { 123 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) { 126 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB)); 139 HexagonMCInstrInfo::hasNewValue(MCII, Inst) 140 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() 145 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst) [all...] |
HexagonMCShuffler.cpp | 36 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); 40 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), 55 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), 60 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); 63 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), 70 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), 101 bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 103 HexagonMCShuffler MCS(MCII, STI, MCB); 151 llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, 179 HexagonMCShuffler MCS(MCII, STI, Attempt); // copy packet to the shuffle [all...] |
HexagonMCELFStreamer.h | 22 std::unique_ptr<MCInstrInfo> MCII; 28 MCII(createHexagonMCInstrInfo()) {}
|
HexagonShuffler.h | 84 HexagonCVIResource(MCInstrInfo const &MCII, unsigned s, MCInst const *id); 103 HexagonInstr(MCInstrInfo const &MCII, MCInst const *id, 105 : ID(id), Extender(Extender), Core(s), CVI(MCII, s, id), 141 MCInstrInfo const &MCII; 160 explicit HexagonShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
|
HexagonAsmBackend.cpp | 36 std::unique_ptr <MCInstrInfo> MCII; 41 OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *), 181 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); 184 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || 185 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && 187 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && 189 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) 316 *MCII, CrntHMI, 317 HexagonMCInstrInfo::getExtendableOperand(*MCII, CrntHMI));
|
HexagonMCELFStreamer.cpp | 52 HexagonMCShuffle(*MCII, STI, *MCB); 59 if (HexagonMCInstrInfo::isDuplex(*MCII, *MCI)) { 61 HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *SubInst); 63 HexagonMCInstrInfo::clampExtended(*MCII, getContext(), *MCI);
|
HexagonMCTargetDesc.h | 44 MCCodeEmitter *createHexagonMCCodeEmitter(const MCInstrInfo &MCII,
|
/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
AMDGPUMCTargetDesc.h | 31 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, 35 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
|
AMDGPUMCTargetDesc.cpp | 73 static MCCodeEmitter *createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII, 77 return createSIMCCodeEmitter(MCII, STI, Ctx); 79 return createR600MCCodeEmitter(MCII, STI, Ctx);
|
SIMCCodeEmitter.cpp | 62 const MCInstrInfo &MCII; 67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 69 : MCII(mcii), STI(sti), Ctx(ctx) { } 125 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, 128 return new SIMCCodeEmitter(MCII, STI, Ctx); 260 return MCII.get(MI.getOpcode()).TSFlags & SI_INSTR_FLAGS_ENCODING_MASK;
|
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
AMDGPUMCTargetDesc.h | 38 MCCodeEmitter *createR600MCCodeEmitter(const MCInstrInfo &MCII, 42 MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
|
R600MCCodeEmitter.cpp | 36 const MCInstrInfo &MCII; 40 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri) 41 : MCII(mcii), MRI(mri) { } 82 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, 85 return new R600MCCodeEmitter(MCII, MRI); 91 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 170 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
|
SIMCCodeEmitter.cpp | 37 const MCInstrInfo &MCII; 47 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri, 49 : MCII(mcii), MRI(mri) { } 72 MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII, 75 return new SIMCCodeEmitter(MCII, MRI, Ctx); 186 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); 263 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
/external/llvm/lib/Target/BPF/MCTargetDesc/ |
BPFMCTargetDesc.h | 38 MCCodeEmitter *createBPFMCCodeEmitter(const MCInstrInfo &MCII, 41 MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
|
/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
SparcMCTargetDesc.h | 37 MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
|
/external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
WebAssemblyMCTargetDesc.h | 41 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII,
|
WebAssemblyMCCodeEmitter.cpp | 62 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII, 65 return new WebAssemblyMCCodeEmitter(MCII, MRI, Ctx);
|
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsMCTargetDesc.h | 38 MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, 41 MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
|
/external/llvm/lib/Target/Hexagon/ |
HexagonMCInstLower.cpp | 30 void HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, 73 void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI, 143 HexagonMCInstrInfo::extendIfNeeded(AP.OutContext, MCII, MCB, *MCI,
|
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCTargetDesc.h | 59 MCCodeEmitter *createARMLEMCCodeEmitter(const MCInstrInfo &MCII, 63 MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
|