| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 187 /// MERGE_VALUES - This node takes multiple discrete operands and returns
192 MERGE_VALUES,
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 146 case ISD::MERGE_VALUES: return "merge_values";
|
| InstrEmitter.cpp | [all...] |
| SelectionDAGBuilder.cpp | 710 return DAG.getNode(ISD::MERGE_VALUES, dl, DAG.getVTList(ValueVTs), Values);
[all...] |
| LegalizeVectorTypes.cpp | 51 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break;
592 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break;
[all...] |
| LegalizeFloatTypes.cpp | 70 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break;
[all...] |
| LegalizeIntegerTypes.cpp | 52 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break;
[all...] |
| LegalizeDAG.cpp | 528 // Callers expect a MERGE_VALUES node.
[all...] |
| ScheduleDAGRRList.cpp | 677 case ISD::MERGE_VALUES:
[all...] |
| SelectionDAG.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | [all...] |
