/external/llvm/lib/Target/ARM/ |
ARMLoadStoreOptimizer.cpp | 136 ARMCC::CondCodes Pred, unsigned PredReg); 139 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, 143 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, 444 ARMCC::CondCodes Pred, unsigned PredReg) { 512 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); 530 .addReg(Base).addImm(WordOffset * 4).addImm(Pred).addReg(PredReg); 579 bool BaseKill, unsigned Opcode, ARMCC::CondCodes Pred, unsigned PredReg, 694 .addImm(Pred).addReg(PredReg); 704 .addImm(Pred).addReg(PredReg); 709 .addImm(Pred).addReg(PredReg); [all...] |
ThumbRegisterInfo.h | 43 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0,
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Thumb2InstrInfo.h | 73 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; 61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); 108 unsigned PredReg = 0; 109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; 219 ARMCC::CondCodes Pred, unsigned PredReg, 224 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 241 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 257 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 268 .addImm((unsigned)Pred).addReg(PredReg).addReg(0 [all...] |
ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, 78 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) 86 ARMCC::CondCodes Pred, unsigned PredReg, 106 unsigned PredReg, unsigned MIFlags) const { 113 PredReg, MIFlags); 116 PredReg, MIFlags);
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Thumb2ITBlockPass.cpp | 184 unsigned PredReg = 0; 185 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg);
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ARMBaseInstrInfo.h | 450 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg); 471 ARMCC::CondCodes Pred, unsigned PredReg, 477 ARMCC::CondCodes Pred, unsigned PredReg,
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MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); 298 MIB.addImm(Pred).addReg(PredReg); 310 MIB.addImm(Pred).addReg(PredReg);
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ARMBaseRegisterInfo.h | 164 unsigned PredReg = 0,
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Thumb2SizeReduction.cpp | 599 unsigned PredReg = 0; 600 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 704 unsigned PredReg = 0; 705 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 800 unsigned PredReg = 0; 801 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); [all...] |
ARMBaseRegisterInfo.cpp | 386 unsigned PredReg, unsigned MIFlags) const { 397 .addImm(0).addImm(Pred).addReg(PredReg) 736 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); 744 Offset, Pred, PredReg, TII); 748 Offset, Pred, PredReg, TII);
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ARMFrameLowering.cpp | 129 unsigned PredReg = 0) { 132 Pred, PredReg, TII, MIFlags); 135 Pred, PredReg, TII, MIFlags); 143 unsigned PredReg = 0) { 145 MIFlags, Pred, PredReg); [all...] |
ARMConstantIslandPass.cpp | [all...] |
ARMExpandPseudoInsts.cpp | [all...] |
ARMBaseInstrInfo.cpp | [all...] |
ARMISelDAGToDAG.cpp | [all...] |
/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCChecker.cpp | 59 unsigned PredReg = Hexagon::NoRegister; 69 PredReg = R; 74 NewPreds.insert(PredReg); 113 Defs[R].insert(PredSense(PredReg, isTrue)); 152 CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue)); 165 Defs[*SRI].insert(PredSense(PredReg, isTrue)); 181 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), 193 NewDefs[*SRI].push_back(NewSense::Def(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI), 217 NewUses[N] = NewSense::Use(PredReg, HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI)); 560 if (Use.IsNVJ && (Def.IsFloat || Def.PredReg != 0) [all...] |
HexagonMCCompound.cpp | 182 unsigned PredReg = Predicate.getReg(); 184 assert((PredReg == Hexagon::P0) || (PredReg == Hexagon::P1) || 185 (PredReg == Hexagon::P2) || (PredReg == Hexagon::P3)); 192 return (PredReg == Hexagon::P0) ? fp0_jump_nt : fp1_jump_nt; 194 return (PredReg == Hexagon::P0) ? fp0_jump_t : fp1_jump_t; 196 return (PredReg == Hexagon::P0) ? tp0_jump_nt : tp1_jump_nt; 198 return (PredReg == Hexagon::P0) ? tp0_jump_t : tp1_jump_t;
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HexagonMCChecker.h | 92 /// PredReg = predicate register, 0 if use/def not predicated, 93 /// Cond = true/false for if(PredReg)/if(!PredReg) respectively, 99 unsigned PredReg; 103 NewSense NS = { /*PredReg=*/ 0, /*IsFloat=*/ false, /*IsNVJ=*/ isNVJ, 108 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ false, /*IsNVJ=*/ false, 113 NewSense NS = { /*PredReg=*/ PR, /*IsFloat=*/ Float, /*IsNVJ=*/ false,
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HexagonMCDuplexInfo.cpp | 181 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; 475 PredReg = MCI.getOperand(1).getReg(); // P0 477 Hexagon::P0 == PredReg && minConstant(MCI, 2) == 0) { [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonInstrInfo.h | 339 bool predCanBeUsedAsDotNew(const MachineInstr *MI, unsigned PredReg) const; 375 bool getPredReg(ArrayRef<MachineOperand> Cond, unsigned &PredReg,
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HexagonGenPredicate.cpp | 97 bool isScalarPred(Register PredReg); 304 bool HexagonGenPredicate::isScalarPred(Register PredReg) { 306 WorkQ.push(PredReg);
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HexagonInstrInfo.cpp | [all...] |
HexagonHardwareLoops.cpp | 613 unsigned PredReg, PredPos, PredRegFlags; 614 if (!TII->getPredReg(Cond, PredReg, PredPos, PredRegFlags)) 616 MachineInstr *CondI = MRI->getVRegDef(PredReg); [all...] |