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  /external/valgrind/none/tests/ppc32/
opcodes.h 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
33 "(" #RB "<<" X20_RB_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
46 #define DCBT_S(RA, RB, TH) X20(DCBT_OPCODE, TH, RA, RB, DCBT_XO, DCBT_RES)
47 #define ASM_DCBT(RA, RB, TH) __asm__ __volatile__ (DCBT_S(RA, RB, TH))
53 #define DCBTST_S(RA, RB, TH) X20(DCBTST_OPCODE, TH, RA, RB, DCBTST_XO, DCBTST_RES
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data-cache-instructions.c 20 register char *rb asm ("r14");
30 rb = test_block;
32 memset(rb, 0xff, test_block_size);
33 asm volatile ("dcbzl 0, %[RB]" : : [RB] "r" (rb));
34 for (block_size = 0, p = rb; (p - rb) < test_block_size; p++)
50 asm volatile ("dcbzl %[RA], %[RB]" : : [RA] "r" (0), [RB] "r" (addr))
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  /external/clang/lib/Rewrite/
HTMLRewrite.cpp 57 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E,
61 RB.InsertTextAfter(B, StartTag);
62 RB.InsertTextBefore(E, EndTag);
76 RB.InsertTextBefore(LastNonWhiteSpace+1, EndTag);
95 RB.InsertTextAfter(i, StartTag);
115 RewriteBuffer &RB = R.getEditBuffer(FID);
128 RB.ReplaceText(FilePos, 1, "&nbsp;");
132 RB.ReplaceText(FilePos, 1, "<hr>");
141 RB.ReplaceText(FilePos, 1,
145 RB.ReplaceText(FilePos, 1, StringRef(" ", NumSpaces))
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Rewriter.cpp 143 const RewriteBuffer &RB = I->second;
144 EndOff = RB.getMappedOffset(EndOff, opts.IncludeInsertsAtEndOfRange);
145 StartOff = RB.getMappedOffset(StartOff, !opts.IncludeInsertsAtBeginOfRange);
195 const RewriteBuffer &RB = I->second;
196 EndOff = RB.getMappedOffset(EndOff, true);
197 StartOff = RB.getMappedOffset(StartOff);
204 RewriteBuffer::iterator Start = RB.begin();
381 RewriteBuffer &RB = getEditBuffer(FID);
389 RB.InsertText(offs, indent, /*InsertAfter=*/false);
  /external/clang/test/Layout/
ms-x86-alias-avoidance-padding.cpp 302 struct RB { char c; };
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
309 struct RX3 : RA { RB a; };
311 struct RX5 { RA a; RB b; };
312 struct RX6 : virtual RV { RB a; };
324 // CHECK-NEXT: 0 | struct RB (base)
337 // CHECK-X64-NEXT: 0 | struct RB (base)
350 // CHECK-NEXT: 0 | struct RB (base)
360 // CHECK-X64-NEXT: 0 | struct RB (base
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  /toolchain/binutils/binutils-2.25/opcodes/
ppc-opc.c 495 /* The RB field in an X, XO, M, or MDS form instruction. */
496 #define RB RAOPT + 1
500 /* The RB field in an X form instruction when it must be the same as
503 #define RBS RB + 1
506 /* The RB field in an lswx instruction, which has special value
511 /* The RB field of the dccci and iccci instructions, which are optional. */
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or1k-opc.c 197 /* l.jr $rB */
200 { { MNEM, ' ', OP (RB), 0 } },
203 /* l.jalr $rB */
206 { { MNEM, ' ', OP (RB), 0 } },
287 /* l.mtspr $rA,$rB,${uimm16-split} */
290 { { MNEM, ' ', OP (RA), ',', OP (RB), ',', OP (UIMM16_SPLIT), 0 } },
335 /* l.sw ${simm16-split}($rA),$rB */
338 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } },
341 /* l.sb ${simm16-split}($rA),$rB */
344 { { MNEM, ' ', OP (SIMM16_SPLIT), '(', OP (RA), ')', ',', OP (RB), 0 } }
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or1k-opinst.c 61 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
69 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
122 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
188 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 },
198 { INPUT, "rB", HW_H_GPR, CGEN_MODE_UDI, OP_ENT (RB), 0, 0 }
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xstormy16-opc.c 355 /* movf$ws2 $Rdm,($Rb,$Rs,$imm12) */
358 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', 0 } },
361 /* movf$ws2 $Rdm,($Rb,$Rs++,$imm12) */
364 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', 0 } },
367 /* movf$ws2 $Rdm,($Rb,--$Rs,$imm12) */
370 { { MNEM, OP (WS2), ' ', OP (RDM), ',', '(', OP (RB), ',', '-', '-', OP (RS), ',', OP (IMM12), ')', 0 } },
373 /* movf$ws2 ($Rb,$Rs,$imm12),$Rdm */
376 { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), ',', OP (IMM12), ')', ',', OP (RDM), 0 } },
379 /* movf$ws2 ($Rb,$Rs++,$imm12),$Rdm */
382 { { MNEM, OP (WS2), ' ', '(', OP (RB), ',', OP (RS), '+', '+', ',', OP (IMM12), ')', ',', OP (RDM), 0 } }
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  /external/clang/lib/Frontend/Rewrite/
RewriteMacros.cpp 95 RewriteBuffer &RB = Rewrite.getEditBuffer(SM.getMainFileID());
134 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//");
140 RB.InsertTextAfter(SM.getFileOffset(RawTok.getLocation()), "//");
170 RB.InsertTextAfter(RawOffs, &" /*"[HasSpace]);
188 RB.InsertTextBefore(EndPos, "*/");
204 RB.InsertTextBefore(InsertPos, Expansion);
  /external/clang/include/clang/Rewrite/Core/
HTMLRewrite.h 47 void HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E,
  /external/valgrind/tests/
power_insn_available.c 45 register char *rb asm ("r14");
55 rb = test_block;
61 asm volatile ("dcbzl 0, %[RB]" : : [RB] "r" (rb));
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/
rex.s 25 rex.RB
rex.d 27 [ ]*[0-9a-f]+:[ ]+45[ ]+rex.RB
  /external/opencv3/3rdparty/libtiff/
tif_color.c 178 #define Code2V(c, RB, RW, CR) ((((c)-(int32)(RB))*(float)(CR))/(float)(((RW)-(RB)) ? ((RW)-(RB)) : 1))
  /external/pdfium/third_party/libtiff/
tif_color.c 178 #define Code2V(c, RB, RW, CR) ((((c)-(int32)(RB))*(float)(CR))/(float)(((RW)-(RB)) ? ((RW)-(RB)) : 1))
  /libcore/luni/src/test/java/libcore/java/util/
EnumSetTest.java 103 FE, CO, NI, CU, ZN, GA, GE, AS, SE, BR, KR, RB, SR, Y, ZR, NB, MO, TC, RU, RH, PD, AG, CD,
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ilp32/
rex.d 28 [ ]*[0-9a-f]+:[ ]+45[ ]+rex.RB
  /external/clang/tools/arcmt-test/
arcmt-test.cpp 144 for (const auto &RB : PPOpts.RemappedFileBuffers)
145 OS << RB.second->getBuffer();
  /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mt/
msys.s 77 ; cbrb operand: cb, rb
79 fbcb R0,#0,#0,#0,#0,#rb,#0,#0,#0 ; rb = 1
81 fbcb R0,#0,#0,#0,#0,#RB,#0,#0,#0
  /external/llvm/lib/Target/Hexagon/
HexagonVLIWPacketizer.cpp 218 MachineBasicBlock::iterator RB = Begin;
219 while (RB != End && HII->isSchedulingBoundary(RB, &MB, MF))
220 ++RB;
223 MachineBasicBlock::iterator RE = RB;
229 // If RB == End, then RE == End.
230 if (RB != End)
231 Packetizer.PacketizeMIs(&MB, RB, RE);
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HexagonGenInsert.cpp 218 BitValueOrdering(const RegisterOrdering &RB) : BaseOrd(RB) {}
486 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
580 void HexagonGenInsert::buildOrderingBT(RegisterOrdering &RB,
583 // ordering RB), and then sort it using the RegisterCell comparator.
584 BitValueOrdering BVO(RB);
588 for (RegisterOrdering::iterator I = RB.begin(), E = RB.end(); I != E; ++I)
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  /external/skia/gm/
image.cpp 112 RB = W * 4 + 8,
116 fBufferSize = RB * H;
174 SkAutoTUnref<SkSurface> surf0(SkSurface::NewRasterDirect(info, fBuffer, RB));
  /external/clang/lib/Frontend/
ASTUnit.cpp 251 for (const auto &RB : PPOpts.RemappedFileBuffers)
252 delete RB.second;
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  /external/clang/include/clang/AST/
ExprObjC.h 785 ObjCMethodDecl *setMethod, SourceLocation RB)
792 RBracket(RB),
805 SourceLocation RB);
808 void setRBracket(SourceLocation RB) { RBracket = RB; }
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