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    Searched refs:REG_FPU_OFFSET (Results 1 - 5 of 5) sorted by null

  /external/google-breakpad/src/third_party/libdisasm/
ia32_settings.c 11 REG_DWORD_OFFSET, REG_SEG_OFFSET, REG_FPU_OFFSET,
ia32_reg.c 55 { REG_FPU_OFFSET, 0 }, /* mm0 : 18 */
56 { REG_FPU_OFFSET + 1, 0 }, /* mm1 : 19 */
57 { REG_FPU_OFFSET + 2, 0 }, /* mm2 : 20 */
58 { REG_FPU_OFFSET + 3, 0 }, /* mm3 : 21 */
59 { REG_FPU_OFFSET + 4, 0 }, /* mm4 : 22 */
60 { REG_FPU_OFFSET + 5, 0 }, /* mm5 : 23 */
61 { REG_FPU_OFFSET + 6, 0 }, /* mm6 : 24 */
62 { REG_FPU_OFFSET + 7, 0 } /* mm7 : 25 */
159 /* REG_FPU_OFFSET */
ia32_reg.h 24 #define REG_FPU_OFFSET 73 /* 9 * 8 + 1 */
ia32_implicit.c 112 {{ OP_R | OP_W, REG_FPU_OFFSET }, {0}}; /* f2xm1 */
120 {{ OP_R, REG_FPU_OFFSET }, {0}}; /* fcom */
124 {{ OP_R, REG_FPU_OFFSET }, {0}}; /* fpatan */
129 {{ OP_R | OP_W, REG_FPU_OFFSET },
130 { OP_R, REG_FPU_OFFSET + 1 }, {0}}; /* fprem */
137 {{ OP_R, REG_FPU_OFFSET },
138 { OP_R | OP_W, REG_FPU_OFFSET + 1 }, {0}}; /* faddp */
142 {{ OP_R, REG_FPU_OFFSET },
143 { OP_R, REG_FPU_OFFSET + 1 }, {0}}; /* fucompp */
ia32_operand.c 208 op_value + REG_FPU_OFFSET );

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