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    Searched refs:RecVec (Results 1 - 7 of 7) sorted by null

  /external/llvm/utils/TableGen/
CodeGenSchedule.h 30 typedef std::vector<Record*> RecVec;
36 void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
56 RecVec Aliases;
100 RecVec PredTerm;
143 RecVec InstRWs;
186 RecVec ItinDefList;
190 RecVec ItinRWDefs;
193 RecVec WriteResDefs
    [all...]
CodeGenSchedule.cpp 133 RecVec ProcRecords = Records.getAllDerivedDefinitions("Processor");
173 static void scanSchedRW(Record *RWDef, RecVec &RWDefs,
180 RecVec Seq = RWDef->getValueAsListOfDefs("Writes");
186 RecVec Vars = RWDef->getValueAsListOfDefs("Variants");
189 RecVec Selected = (*VI)->getValueAsListOfDefs("Selected");
206 RecVec SWDefs, SRDefs;
211 RecVec RWs = SchedDef->getValueAsListOfDefs("SchedRW");
222 RecVec InstRWDefs = Records.getAllDerivedDefinitions("InstRW");
225 RecVec RWDefs = (*OI)->getValueAsListOfDefs("OperandReadWrites");
237 RecVec ItinRWDefs = Records.getAllDerivedDefinitions("ItinRW")
    [all...]
SubtargetEmitter.cpp 92 void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
622 RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources");
763 void SubtargetEmitter::ExpandProcResources(RecVec &PRVec,
770 RecVec SubResources;
795 RecVec SuperResources = (*PRI)->getValueAsListOfDefs("Resources");
890 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
    [all...]
RegisterInfoEmitter.cpp     [all...]
CodeGenRegisters.cpp 677 const SetTheory::RecVec *Elements = RegBank.getSets().expand(R);
    [all...]
  /external/llvm/include/llvm/TableGen/
SetTheory.h 65 typedef std::vector<Record*> RecVec;
94 typedef std::map<Record*, RecVec> ExpandMap;
136 const RecVec *expand(Record *Set);
  /external/llvm/lib/TableGen/
SetTheory.cpp 26 typedef SetTheory::RecVec RecVec;
220 if (const RecVec *Result = ST.expand(Rec))
275 if (const RecVec *Result = expand(Def->getDef()))
298 const RecVec *SetTheory::expand(Record *Set) {
313 RecVec &EltVec = Expansions[Set];

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