| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/ |
| 386.s | 8 SETCC AX
9 SETCC foo+4(SB)
|
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| 386.s | 8 SETCC AX
9 SETCC foo+4(SB)
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | [all...] |
| X86ISelLowering.cpp | 80 // X86 is weird. It always uses i8 for shift amounts and setcc results.
421 setOperationAction(ISD::SETCC , MVT::i8 , Custom);
422 setOperationAction(ISD::SETCC , MVT::i16 , Custom);
423 setOperationAction(ISD::SETCC , MVT::i32 , Custom);
424 setOperationAction(ISD::SETCC , MVT::f32 , Custom);
425 setOperationAction(ISD::SETCC , MVT::f64 , Custom);
426 setOperationAction(ISD::SETCC , MVT::f80 , Custom);
427 setOperationAction(ISD::SETCC , MVT::f128 , Custom);
433 setOperationAction(ISD::SETCC , MVT::i64 , Custom);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIISelLowering.cpp | 62 setTargetDAGCombine(ISD::SETCC);
318 ISD::SETCC,
384 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
403 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
409 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
415 case ISD::SETCC: {
422 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
|
| R600ISelLowering.cpp | 48 setOperationAction(ISD::SETCC, MVT::i32, Custom);
252 case ISD::SETCC: return LowerSETCC(Op, DAG);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 50 /// SetCC - Operand 0 is condition code, and operand 1 is the flag
52 SETCC,
|
| MSP430ISelLowering.cpp | 108 setOperationAction(ISD::SETCC, MVT::i8, Custom);
109 setOperationAction(ISD::SETCC, MVT::i16, Custom);
192 case ISD::SETCC: return LowerSETCC(Op, DAG);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 350 /// Much like the scalar select and setcc, each bit in the condition selects
363 /// SetCC operator - This evaluates to a true value iff the condition is
369 SETCC,
371 /// Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but
569 /// compare, rather than as a combined SetCC node. The operands in order
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorTypes.cpp | 66 case ISD::SETCC: R = ScalarizeVecRes_SETCC(N); break;
301 if (Cond->getOpcode() == ISD::SETCC) {
362 // Turn it into a scalar SETCC.
363 return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
403 // Turn it into a scalar SETCC.
404 SDValue Res = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS,
617 case ISD::SETCC:
[all...] |
| LegalizeVectorOps.cpp | 293 case ISD::SETCC:
718 case ISD::SETCC:
[all...] |
| DAGCombiner.cpp | 711 // Return true if this node is a setcc, or is a select_cc
713 // equivalent to a setcc. Also, set the incoming LHS, RHS, and CC references to
718 if (N.getOpcode() == ISD::SETCC) {
740 /// Return true if this is a SetCC-equivalent operation with only one use.
[all...] |
| TargetLowering.cpp | 122 /// shared among BR_CC, SELECT_CC, and SETCC handlers.
128 && "Unsupported setcc type!");
205 default: llvm_unreachable("Do not know how to soften this setcc!");
222 ISD::SETCC, dl,
228 ISD::SETCC, dl,
[all...] |
| LegalizeDAG.cpp | 55 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this
56 /// will attempt merge setcc and brc instructions into brcc's.
[all...] |
| /prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/x86/ |
| anames.go | 192 "SETCC",
|
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/x86/ |
| anames.go | 189 "SETCC",
|
| /prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/x86/ |
| anames.go | 192 "SETCC",
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/x86/ |
| anames.go | 189 "SETCC",
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 106 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
107 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
263 setTargetDAGCombine(ISD::SETCC);
[all...] |
| R600ISelLowering.cpp | 67 setOperationAction(ISD::SETCC, MVT::v4i32, Expand);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
83 setOperationAction(ISD::SETCC, MVT::i32, Expand);
84 setOperationAction(ISD::SETCC, MVT::f32, Expand);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 79 setTargetDAGCombine(ISD::SETCC);
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
285 setOperationAction(ISD::SETCC, Ty, Legal);
322 setOperationAction(ISD::SETCC, Ty, Legal);
[all...] |
| MipsISelLowering.cpp | 229 // setcc operations results (slt, sgt, ...).
264 // Used by legalize types to correctly generate the setcc result.
265 // Without this, every float setcc comes with a AND/OR with the result,
268 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
282 setOperationAction(ISD::SETCC, MVT::f32, Custom);
283 setOperationAction(ISD::SETCC, MVT::f64, Custom);
546 // Creates and returns an FPCmp node from a setcc node.
547 // Returns Op if setcc is not a floating point comparison.
549 // must be a SETCC node
550 if (Op.getOpcode() != ISD::SETCC)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 69 // AArch64 doesn't have comparisons which set GPRs or setcc instructions, so
114 setOperationAction(ISD::SETCC, MVT::i32, Custom);
115 setOperationAction(ISD::SETCC, MVT::i64, Custom);
116 setOperationAction(ISD::SETCC, MVT::f32, Custom);
117 setOperationAction(ISD::SETCC, MVT::f64, Custom);
165 setOperationAction(ISD::SETCC, MVT::f128, Custom);
275 setOperationAction(ISD::SETCC, MVT::f16, Promote);
345 setOperationAction(ISD::SETCC, MVT::v4f16, Expand);
378 setOperationAction(ISD::SETCC, MVT::v8f16, Expand);
550 setOperationAction(ISD::SETCC, MVT::v1f64, Expand)
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
