| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDGPUISelLowering.h | 121 SMIN,
|
| AMDGPUISelLowering.cpp | 136 return DAG.getNode(AMDGPUISD::SMIN, DL, VT, Op.getOperand(1),
349 NODE_NAME_CASE(SMIN)
|
| /external/llvm/lib/Target/X86/ |
| X86IntrinsicsInfo.h | 265 X86_INTRINSIC_DATA(avx2_pmins_b, INTR_TYPE_2OP, ISD::SMIN, 0),
266 X86_INTRINSIC_DATA(avx2_pmins_d, INTR_TYPE_2OP, ISD::SMIN, 0),
267 X86_INTRINSIC_DATA(avx2_pmins_w, INTR_TYPE_2OP, ISD::SMIN, 0),
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ISDOpcodes.h | 322 SMIN, SMAX, UMIN, UMAX,
[all...] |
| SelectionDAG.h | [all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| rtl.def | 477 unsigned forms. (We cannot use MIN for SMIN because it conflicts
483 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
[all...] |
| genrtl.h | 997 gen_rtx_fmt_ee (SMIN, (MODE), (ARG0), (ARG1))
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 206 case ISD::SMIN: return "smin";
|
| LegalizeVectorOps.cpp | 330 case ISD::SMIN:
[all...] |
| LegalizeVectorTypes.cpp | 114 case ISD::SMIN:
687 case ISD::SMIN:
[all...] |
| SelectionDAG.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| LegalizeIntegerTypes.cpp | 78 case ISD::SMIN:
[all...] |
| SelectionDAGBuilder.cpp | [all...] |
| DAGCombiner.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 258 setTargetDAGCombine(ISD::SMIN);
[all...] |
| AMDGPUISelLowering.cpp | 280 setOperationAction(ISD::SMIN, MVT::i32, Legal);
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | 793 setOperationAction(ISD::SMIN, VT, Expand);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelLowering.cpp | 697 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 148 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
[all...] |
