/external/llvm/lib/Target/ARM/ |
ARMTargetTransformInfo.cpp | 405 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, 409 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, 413 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, 417 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, 422 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, 426 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, 430 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, 434 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
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ARMISelLowering.cpp | 143 setOperationAction(ISD::UREM, VT, Expand); [all...] |
/prebuilts/go/darwin-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm64/ |
anames.go | 235 "UREM",
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/prebuilts/go/darwin-x86/src/cmd/internal/obj/arm64/ |
anames.go | 232 "UREM",
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/prebuilts/go/linux-x86/pkg/bootstrap/src/bootstrap/internal/obj/arm64/ |
anames.go | 235 "UREM",
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/prebuilts/go/linux-x86/src/cmd/internal/obj/arm64/ |
anames.go | 232 "UREM",
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/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::UREM, MVT::i32, Expand);
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AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines 725 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1);
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/external/llvm/lib/Target/Mips/ |
MipsFastISel.cpp | [all...] |
MipsSEISelLowering.cpp | 171 setOperationAction(ISD::UREM, MVT::i32, Legal); 218 setOperationAction(ISD::UREM, MVT::i64, Legal); 273 setOperationAction(ISD::UREM, Ty, Legal); [all...] |
MipsISelLowering.cpp | 317 setOperationAction(ISD::UREM, MVT::i32, Expand); 321 setOperationAction(ISD::UREM, MVT::i64, Expand); [all...] |
/external/llvm/lib/CodeGen/ |
TargetLoweringBase.cpp | [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 152 setOperationAction(ISD::UREM, MVT::i8, Expand); 158 setOperationAction(ISD::UREM, MVT::i16, Expand); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGBuilder.h | 781 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } [all...] |
SelectionDAGDumper.cpp | 183 case ISD::UREM: return "urem";
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FastISel.cpp | 438 // Transform "urem x, pow2" -> "and x, pow2-1". 439 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && [all...] |
LegalizeVectorOps.cpp | 267 case ISD::UREM: [all...] |
LegalizeVectorTypes.cpp | 128 case ISD::UREM: 684 case ISD::UREM: [all...] |
SelectionDAG.cpp | [all...] |
LegalizeIntegerTypes.cpp | 125 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break; [all...] |
/external/llvm/lib/Target/BPF/ |
BPFISelLowering.cpp | 120 setOperationAction(ISD::UREM, MVT::i64, Expand);
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/external/llvm/lib/Target/AArch64/ |
AArch64FastISel.cpp | [all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUISelLowering.cpp | 273 setOperationAction(ISD::UREM, MVT::i32, Expand); 314 setOperationAction(ISD::UREM, VT, Expand); [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonISelLowering.cpp | [all...] |