| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 33 Inst.addOperand(MCOperand::createReg(Reg));
39 Inst.addOperand(MCOperand::createImm(Val));
45 Inst.addOperand(MCOperand::createFPImm(Val));
51 Inst.addOperand(MCOperand::createExpr(Val));
57 Inst.addOperand(MCOperand::createInst(Val));
62 MCInstBuilder &addOperand(const MCOperand &Op) {
63 Inst.addOperand(Op);
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 539 MI.addOperand(MCOperand::createImm(tmp));
545 MI.addOperand(MCOperand::createImm(0));
579 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
582 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
584 MI.addOperand(MCOperand::createImm(Imm));
618 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
621 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
623 MI.addOperand(MCOperand::createImm(Imm));
660 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID,
663 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID
[all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCCompound.cpp | 222 CompoundInsn->addOperand(Rt);
223 CompoundInsn->addOperand(L.getOperand(1)); // Immediate
224 CompoundInsn->addOperand(R.getOperand(0)); // Jump target
234 CompoundInsn->addOperand(Rt);
235 CompoundInsn->addOperand(Rs);
236 CompoundInsn->addOperand(R.getOperand(0)); // Jump target.
248 CompoundInsn->addOperand(Rs);
249 CompoundInsn->addOperand(Rt);
250 CompoundInsn->addOperand(R.getOperand(1));
261 CompoundInsn->addOperand(Rs)
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 544 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
549 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
554 Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
559 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
578 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
583 Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
588 Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
593 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
598 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
603 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]))
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600ISelLowering.cpp | 66 .addOperand(MI->getOperand(0))
67 .addOperand(MI->getOperand(1))
77 .addOperand(MI->getOperand(0))
78 .addOperand(MI->getOperand(1))
89 .addOperand(MI->getOperand(0))
90 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(0))
135 .addOperand(MI->getOperand(1))
139 .addOperand(MI->getOperand(0))
161 .addOperand(MI->getOperand(3)
[all...] |
| SIISelLowering.cpp | 83 .addOperand(MI->getOperand(0))
84 .addOperand(MI->getOperand(1))
87 .addOperand(MI->getOperand(1))
88 .addOperand(MI->getOperand(1))
98 .addOperand(MI->getOperand(0))
99 .addOperand(MI->getOperand(1))
102 .addOperand(MI->getOperand(1))
103 .addOperand(MI->getOperand(1))
113 .addOperand(MI->getOperand(0))
114 .addOperand(MI->getOperand(1)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::createImm(0));
40 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::createReg(0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createReg(ARM::R0));
46 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
47 NopInst.addOperand(MCOperand::createReg(0));
48 NopInst.addOperand(MCOperand::createReg(0));
|
| Thumb1InstrInfo.cpp | 30 NopInst.addOperand(MCOperand::createReg(ARM::R8));
31 NopInst.addOperand(MCOperand::createReg(ARM::R8));
32 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
33 NopInst.addOperand(MCOperand::createReg(0));
|
| ARMExpandPseudoInsts.cpp | 85 UseMI.addOperand(MO);
87 DefMI.addOperand(MO);
403 MIB.addOperand(MI.getOperand(OpIdx++));
406 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
410 MIB.addOperand(MI.getOperand(OpIdx++));
420 MIB.addOperand(MI.getOperand(OpIdx++));
421 MIB.addOperand(MI.getOperand(OpIdx++));
428 MIB.addOperand(MO);
455 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 108 Hexagon::C6)->addOperand(Op3);
112 NewMI->addOperand(Op0);
113 NewMI->addOperand(Op1);
114 NewMI->addOperand(Op4);
115 NewMI->addOperand(MachineOperand::CreateReg(Hexagon::M0,
119 NewMI->addOperand(Op2);
151 Hexagon::C6)->addOperand(Op4);
155 NewMI->addOperand(Op1);
156 NewMI->addOperand(Op0);
157 NewMI->addOperand(Op2)
[all...] |
| HexagonAsmPrinter.cpp | 280 TmpInst.addOperand(Reg);
281 TmpInst.addOperand(MCOperand::createExpr(
299 TmpInst.addOperand(Reg);
300 TmpInst.addOperand(MCOperand::createExpr(
312 MappedInst.addOperand(Ps);
374 TmpInst.addOperand(MappedInst.getOperand(0));
375 TmpInst.addOperand(MappedInst.getOperand(1));
380 TmpInst.addOperand(MappedInst.getOperand(0));
381 TmpInst.addOperand(MappedInst.getOperand(1));
384 TmpInst.addOperand(MCOperand::createExpr(Sub))
[all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 55 Inst.addOperand(MCOperand::createReg(RegNo));
129 Inst.addOperand(MCOperand::createImm(Imm));
137 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
211 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm) * 2 + Address));
232 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
233 Inst.addOperand(MCOperand::createImm(Disp));
242 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
243 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
253 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base]));
254 Inst.addOperand(MCOperand::createImm(Disp))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 69 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
84 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
89 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
94 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
100 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
105 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
112 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
118 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
125 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
132 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags))
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerI1Copies.cpp | 124 .addOperand(Dst)
132 .addOperand(Dst)
135 .addOperand(Src);
140 .addOperand(Dst)
141 .addOperand(Src)
|
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 171 MI.addOperand(MCOperand::createInst(Inst));
310 MI.addOperand(OPLow);
311 MI.addOperand(OPHigh);
476 Inst.addOperand(MCOperand::createReg(Table[RegNo]));
578 Inst.addOperand(MCOperand::createReg(Register));
602 Inst.addOperand(MCOperand::createReg(Register));
620 Inst.addOperand(MCOperand::createReg(Register));
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 762 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
765 TmpInst.addOperand(MCOperand::createExpr(HiSym));
771 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
772 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
775 TmpInst.addOperand(MCOperand::createExpr(LoSym));
781 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
782 TmpInst.addOperand(MCOperand::createReg(Mips::GP));
783 TmpInst.addOperand(MCOperand::createReg(RegNo));
822 Inst.addOperand(MCOperand::createReg(RegOrOffset));
823 Inst.addOperand(MCOperand::createReg(Mips::GP))
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86Operand.h | 379 Inst.addOperand(MCOperand::createImm(CE->getValue()));
381 Inst.addOperand(MCOperand::createExpr(Expr));
386 Inst.addOperand(MCOperand::createReg(getReg()));
417 Inst.addOperand(MCOperand::createReg(RegNo));
430 Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
431 Inst.addOperand(MCOperand::createImm(getMemScale()));
432 Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
434 Inst.addOperand(MCOperand::createReg(getMemSegReg()));
441 Inst.addOperand(MCOperand::createImm(CE->getValue()));
443 Inst.addOperand(MCOperand::createExpr(getMemDisp()))
[all...] |
| /external/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 354 Inst.addOperand(MCOperand::createReg(getReg()));
359 Inst.addOperand(MCOperand::createExpr(getImm()));
367 Inst.addOperand(MCOperand::createExpr(Expr));
372 Inst.addOperand(MCOperand::createExpr(Expr));
377 Inst.addOperand(MCOperand::createImm(Extended));
557 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
563 Inst.addOperand(MCOperand::createImm(CE->getValue() * 64));
768 NewInst.addOperand(MCOperand::createExpr(
772 NewInst.addOperand(I);
844 MCB.addOperand(MCOperand::createImm(0))
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 470 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
479 TmpInst.addOperand(Dest);
503 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
504 Adrp.addOperand(SymTLSDesc);
509 Ldr.addOperand(MCOperand::createReg(AArch64::X1));
510 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
511 Ldr.addOperand(SymTLSDescLo12);
512 Ldr.addOperand(MCOperand::createImm(0));
517 Add.addOperand(MCOperand::createReg(AArch64::X0));
518 Add.addOperand(MCOperand::createReg(AArch64::X0))
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZLongBranch.cpp | 352 .addOperand(MI->getOperand(0))
353 .addOperand(MI->getOperand(1))
358 .addOperand(MI->getOperand(2));
371 .addOperand(MI->getOperand(0))
372 .addOperand(MI->getOperand(1));
375 .addOperand(MI->getOperand(2))
376 .addOperand(MI->getOperand(3));
|
| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 117 .addOperand(Dest)
118 .addOperand(Src)
281 .addOperand(MI->getOperand(0))
282 .addOperand(MI->getOperand(1));
372 .addOperand(Dst)
373 .addOperand(Src1)
374 .addOperand(Src2);
382 .addOperand(Dst)
383 .addOperand(SrcR)
|
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsMCInstLower.cpp | 127 Inst.addOperand(Opnd0);
128 Inst.addOperand(Opnd1);
130 Inst.addOperand(Opnd2);
176 OutMI.addOperand(LowerOperand(MI->getOperand(0)));
179 OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
192 OutMI.addOperand(LowerOperand(MO));
196 OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
237 OutMI.addOperand(MCOp);
|
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 272 Inst.addOperand(MCOperand::createReg(Register));
301 Inst.addOperand(MCOperand::createReg(Register));
322 Inst.addOperand(MCOperand::createReg(Register));
343 Inst.addOperand(MCOperand::createReg(Register));
364 Inst.addOperand(MCOperand::createReg(Register));
385 Inst.addOperand(MCOperand::createReg(Register));
397 Inst.addOperand(MCOperand::createReg(Register));
418 Inst.addOperand(MCOperand::createReg(Register));
431 Inst.addOperand(MCOperand::createReg(Register));
452 Inst.addOperand(MCOperand::createReg(Register))
[all...] |
