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    Searched refs:bankw (Results 1 - 7 of 7) sorted by null

  /external/mesa3d/src/gallium/winsys/radeon/drm/
radeon_winsys.h 205 unsigned *bankw, unsigned *bankh,
225 unsigned bankw, unsigned bankh,
radeon_drm_bo.c 713 unsigned *bankw, unsigned *bankh,
737 if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) {
738 *bankw = (args.tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
751 unsigned bankw, unsigned bankh,
781 args.tiling_flags |= (bankw & RADEON_TILING_EG_BANKW_MASK) <<
  /external/libdrm/radeon/
radeon_surface.h 124 * overridden (things lile bankw/bankh on evergreen for
130 uint32_t bankw; member in struct:radeon_surface
radeon_surface.c 670 mtilew = (tilew * surf->bankw * surf_man->hw_info.num_pipes) * surf->mtilea;
755 switch (surf->bankw) {
775 if ((tileb * surf->bankh * surf->bankw) < surf_man->hw_info.group_bytes) {
900 /* compute best tile_split, bankw, bankh, mtilea
914 surf->bankw = 1;
919 if ((tileb * surf->bankh * surf->bankw) >= surf_man->hw_info.group_bytes) {
971 /* bankw or bankh greater than 1 increase alignment requirement, not
972 * sure if it's worth using smaller bankw & bankh to stick with 2D
988 /* use bankw of 1 to minimize width alignment, might be interesting to
991 surf->bankw = 1
    [all...]
  /external/mesa3d/src/gallium/drivers/r600/
evergreen_state.c 993 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local
1053 bankw = tmp->surface.bankw;
1057 bankw = eg_bank_wh(bankw);
1250 unsigned tile_type, macro_aspect, tile_split, bankh, bankw, fmask_bankh, nbanks; local
1441 unsigned macro_aspect, tile_split, bankh, bankw, nbanks; local
    [all...]
r600_texture.c 220 surface->bankw, surface->bankh,
540 &surface.bankw, &surface.bankh,
    [all...]
  /external/mesa3d/src/gallium/drivers/radeonsi/
r600_texture.c 234 surface->bankw, surface->bankh,
607 &surface.bankw, &surface.bankh,

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