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    Searched refs:getRegMask (Results 1 - 21 of 21) sorted by null

  /external/llvm/lib/CodeGen/
DeadMachineInstructionElim.cpp 152 LivePhysRegs.clearBitsNotInMask(MO.getRegMask());
MachineInstr.cpp 251 return getRegMask() == Other.getRegMask();
295 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
423 if (getRegMask()[MaskWord] & (1 << MaskBit)) {
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RegisterScavenging.cpp 315 Candidates.clearBitsNotInMask(MO.getRegMask());
VirtRegMap.cpp 367 MRI->addPhysRegsUsedFromRegMask(MO.getRegMask());
MIRPrinter.cpp 810 auto RegMaskInfo = RegisterMaskIds.find(Op.getRegMask());
RegAllocFast.cpp     [all...]
MachineLICM.cpp 372 PhysRegClobbers.setBitsNotInMask(MO.getRegMask());
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PeepholeOptimizer.cpp     [all...]
LiveIntervalAnalysis.cpp 240 RegMaskBits.push_back(MO.getRegMask());
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MachineVerifier.cpp     [all...]
ScheduleDAGInstrs.cpp     [all...]
  /external/llvm/include/llvm/CodeGen/
MachineOperand.h 483 return clobbersPhysReg(getRegMask(), PhysReg);
486 /// getRegMask - Returns a bit mask of registers preserved by this RegMask
488 const uint32_t *getRegMask() const {
SelectionDAGNodes.h     [all...]
  /external/llvm/lib/Target/AArch64/
AArch64A57FPLoadBalancing.cpp 511 AvailableRegs.clearBitsNotInMask(J.getRegMask());
AArch64CollectLOH.cpp 328 const uint32_t *PreservedRegs = MO.getRegMask();
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AArch64LoadStoreOptimizer.cpp 810 ModifiedRegs.setBitsNotInMask(MO.getRegMask());
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  /external/llvm/lib/CodeGen/MIRParser/
MIParser.cpp 207 const uint32_t *getRegMask(StringRef Identifier);
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MIRParser.cpp 410 MF.getRegInfo().addPhysRegsUsedFromRegMask(MO.getRegMask());
  /external/llvm/lib/CodeGen/SelectionDAG/
InstrEmitter.cpp 393 MIB.addRegMask(RM->getRegMask());
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ScheduleDAGRRList.cpp     [all...]
SelectionDAG.cpp 441 ID.AddPointer(cast<RegisterMaskSDNode>(N)->getRegMask());
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