| /external/llvm/test/MC/AArch64/ |
| neon-scalar-fp-compare.s | 9 fcmeq h10, h11, h12
13 // CHECK: fcmeq h10, h11, h12 // encoding: [0x6a,0x25,0x4c,0x5e]
21 fcmeq h10, h11, #0.0
24 fcmeq h10, h11, #0
28 // CHECK: fcmeq h10, h11, #0.0 // encoding: [0x6a,0xd9,0xf8,0x5e]
31 // CHECK: fcmeq h10, h11, #0.0 // encoding: [0x6a,0xd9,0xf8,0x5e]
39 fcmge h10, h11, h12
43 // CHECK: fcmge h10, h11, h12 // encoding: [0x6a,0x25,0x4c,0x7e]
51 fcmge h10, h11, #0.0
54 fcmge h10, h11, #
[all...] |
| neon-scalar-saturating-rounding-shift.s | 7 sqrshl h10, h11, h12
12 // CHECK: sqrshl h10, h11, h12 // encoding: [0x6a,0x5d,0x6c,0x5e]
20 uqrshl h10, h11, h12
25 // CHECK: uqrshl h10, h11, h12 // encoding: [0x6a,0x5d,0x6c,0x7e]
|
| neon-scalar-saturating-shift.s | 7 sqshl h10, h11, h12
12 // CHECK: sqshl h10, h11, h12 // encoding: [0x6a,0x4d,0x6c,0x5e]
20 uqshl h10, h11, h12
25 // CHECK: uqshl h10, h11, h12 // encoding: [0x6a,0x4d,0x6c,0x7e]
|
| neon-scalar-saturating-add-sub.s | 7 sqadd h10, h11, h12
12 // CHECK: sqadd h10, h11, h12 // encoding: [0x6a,0x0d,0x6c,0x5e]
20 uqadd h10, h11, h12
25 // CHECK: uqadd h10, h11, h12 // encoding: [0x6a,0x0d,0x6c,0x7e]
33 sqsub h10, h11, h12
38 // CHECK: sqsub h10, h11, h12 // encoding: [0x6a,0x2d,0x6c,0x5e]
46 uqsub h10, h11, h12
51 // CHECK: uqsub h10, h11, h12 // encoding: [0x6a,0x2d,0x6c,0x7e]
|
| neon-scalar-mul.s | 9 sqdmulh h10, h11, h12
12 // CHECK: sqdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x5e]
19 sqrdmulh h10, h11, h12
22 // CHECK: sqrdmulh h10, h11, h12 // encoding: [0x6a,0xb5,0x6c,0x7e]
|
| neon-scalar-shift-imm.s | 135 uqshrn b12, h10, #7
136 uqshrn h10, s14, #5
139 // CHECK: uqshrn b12, h10, #7 // encoding: [0x4c,0x95,0x09,0x7f]
140 // CHECK: uqshrn h10, s14, #5 // encoding: [0xca,0x95,0x1b,0x7f]
168 sqshrun b15, h10, #7
172 // CHECK: sqshrun b15, h10, #7 // encoding: [0x4f,0x85,0x09,0x7f]
180 sqrshrun b17, h10, #6
181 sqrshrun h10, s13, #15
184 // CHECK: sqrshrun b17, h10, #6 // encoding: [0x51,0x8d,0x0a,0x7f]
185 // CHECK: sqrshrun h10, s13, #15 // encoding: [0xaa,0x8d,0x11,0x7f
[all...] |
| fullfp16-neon-neg.s | 250 fcmeq h10, h11, h12
252 fcmeq h10, h11, #0.0
254 fcmeq h10, h11, #0
256 fcmge h10, h11, h12
258 fcmge h10, h11, #0.0
260 fcmge h10, h11, #0
262 fcmgt h10, h11, h12
264 fcmgt h10, h11, #0.0
266 fcmgt h10, h11, #0
268 fcmle h10, h11, #0.
[all...] |
| neon-scalar-recip.s | 45 frecpx h18, h10
49 // CHECK: frecpx h18, h10 // encoding: [0x52,0xf9,0xf9,0x5e]
|
| neon-scalar-by-elem-saturating-mul.s | 28 sqdmulh h10, h11, v10.h[4]
34 // CHECK: sqdmulh h10, h11, v10.h[4] // encoding: [0x6a,0xc9,0x4a,0x5f]
|
| neon-diagnostics.s | 234 frecpx s18, h10
238 // CHECK-ERROR: frecpx s18, h10
[all...] |
| basic-a64-instructions.s | [all...] |
| basic-a64-diagnostics.s | [all...] |
| /external/clang/test/Sema/ |
| attr-alias-elf.c | 41 // FIXME: This could be a bit better, h10 is not part of the cycle, it points
43 void h10() __attribute__((alias("g10"))); // expected-error {{alias definition is part of a cycle}}
|
| /external/libvpx/libvpx/vp9/encoder/mips/msa/ |
| vp9_fdct16x16_msa.c | 89 v8i16 h0, h1, h2, h3, h4, h5, h6, h7, h10, h11; local
123 BUTTERFLY_4(tp0, tp1, tp3, tp2, out0, out1, h11, h10);
139 MADD_SHORT(h10, h11, k1, k2, out2, out3);
267 v8i16 h0, h1, h2, h3, h4, h5, h6, h7, h10, h11; local
305 BUTTERFLY_4(tp0, tp1, tp3, tp2, out0, out1, h11, h10);
320 MADD_SHORT(h10, h11, k1, k2, out2, out3);
|
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| idct16x16_msa.c | 331 v8i16 h0, h1, h2, h3, h4, h5, h6, h7, h8, h9, h10, h11; local
383 BUTTERFLY_4(g4, g6, g14, g12, h10, h11, v6, v4);
384 BUTTERFLY_4(h8, h9, h11, h10, out0, out1, h11, h10);
466 MADD_SHORT(h10, h11, k1, k2, out2, out3);
|
| /external/boringssl/src/ssl/test/runner/curve25519/ |
| curve25519.go | 214 // h10 = carry9
216 // Goal: Output h[0]+...+2^255 h10-2^255 q, which is between 0 and 2^255-20.
218 // evidently 2^255 h10-2^255 q = 0.
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| bfin-parse.y | 32 #define DSP32MAC(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
33 bfin_gen_dsp32mac (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
36 #define DSP32MULT(op1, MM, mmod, w1, P, h01, h11, h00, h10, dst, op0, src0, src1, w0) \
37 bfin_gen_dsp32mult (op1, MM, mmod, w1, P, h01, h11, h00, h10, op0, \
741 int h00, h10, h01, h11;
755 h10 = IS_H ($1.s1);
764 h00 = h10 = 0;
768 $$ = DSP32MAC (op1, $2.MM, $2.mod, w1, $1.P, h01, h11, h00, h10,
[all...] |
| tc-bfin.c | 1182 int h01, int h11, int h00, int h10, int op0,
1196 ASSIGN (h10);
1215 int h01, int h11, int h00, int h10, int op0
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| bfin-dis.c | 2949 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); local
3033 int h10 = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask); local
[all...] |
| /external/vixl/test/ |
| test-disasm-a64.cc | [all...] |
