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  /external/gemmlowp/meta/generators/
zip_Nx8_neon.py 29 """Prepares read lanes for the zip operation.
34 zip_lanes: number of lanes to prepare.
41 lanes = []
45 lanes.append(ZipLane(input_address,
50 lanes.append(ZipLane(address_register,
55 return lanes
67 def GenerateClearAggregators(emitter, lanes):
68 for lane in lanes:
72 def GenerateLoadAggregateStore(emitter, lanes, output_address, alignment):
73 """Emit inner loop code for reading N lanes and interweaving them.""
    [all...]
qnt_Nx8_neon.py 26 def BuildName(lanes, leftovers, aligned):
27 name = 'qnt_%dx8' % lanes
35 def LoadAndDuplicateOffsets(emitter, registers, lanes, offsets):
36 if lanes == 1 or lanes == 2 or lanes == 3:
38 for unused_i in range(0, lanes):
47 raise ConfigurationError('Unsupported number of lanes: %d' % lanes)
58 """Prepare lanes for reading unquantized multiplication results.""
    [all...]
mul_Nx8_Mx8_neon.py 22 self.lanes = []
25 self.lanes.append(lane)
28 for i in range(0, len(self.lanes)):
29 registers.FreeRegister(self.lanes[i])
30 self.lanes[i] = None
34 lanes = MulLanes(address)
36 lanes.AddLane(registers.DoubleRegister())
37 return lanes
41 lanes = MulLanes(address)
42 lanes.AddLane(registers.Low(quad_register)
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  /external/v8/test/mjsunit/harmony/
simd.js 25 function isValidSimdString(string, value, type, lanes) {
36 if (laneStrings.length !== lanes)
38 for (var i = 0; i < lanes; i++) {
67 function TestConstructor(type, lanes) {
82 function TestType(type, lanes) {
95 function TestPrototype(type, lanes) {
105 function TestValueOf(type, lanes) {
116 function TestGet(type, lanes) {
127 function TestToBoolean(type, lanes) {
146 function TestToString(type, lanes) {
    [all...]
  /external/v8/src/runtime/
runtime-simd.cc 211 #define CONVERT_SIMD_LANE_ARG_CHECKED(name, index, lanes) \
213 RUNTIME_ASSERT(name >= 0 && name < lanes);
228 lane_type lanes[kLaneCount]; \
230 lanes[i] = op(a->get_lane(i)); \
232 Handle<type> result = isolate->factory()->New##type(lanes);
239 lane_type lanes[kLaneCount]; \
241 lanes[i] = op(a->get_lane(i), b->get_lane(i)); \
243 Handle<type> result = isolate->factory()->New##type(lanes);
250 bool lanes[kLaneCount]; \
252 lanes[i] = a->get_lane(i) op b->get_lane(i);
    [all...]
  /external/v8/test/cctest/
test-simd.cc 16 float lanes[lane_count] = {0}; \
17 Handle<type> a = factory->New##type(lanes); \
18 Handle<type> b = factory->New##type(lanes); \
49 lane_type lanes[lane_count] = {0}; \
50 Handle<type> a = factory->New##type(lanes); \
51 Handle<type> b = factory->New##type(lanes); \
82 bool lanes[lane_count] = {false}; \
83 Handle<type> a = factory->New##type(lanes); \
84 Handle<type> b = factory->New##type(lanes); \
  /external/v8/test/cctest/heap/
test-heap.cc 225 template <typename T, typename LANE_TYPE, int LANES>
226 static void CheckSimdValue(T* value, LANE_TYPE lane_values[LANES],
228 // Check against lane_values, and check that all lanes can be set to
229 // other_value without disturbing the other lanes.
230 for (int i = 0; i < LANES; i++) {
233 for (int i = 0; i < LANES; i++) {
235 for (int j = 0; j < LANES; j++) {
256 float lanes[4] = {1, 2, 3, 4}; local
260 Handle<Float32x4> value = factory->NewFloat32x4(lanes);
262 CheckSimdValue<Float32x4, float, 4>(*value, lanes, 3.14f)
293 int32_t lanes[4] = {1, 2, 3, 4}; local
307 uint32_t lanes[4] = {1, 2, 3, 4}; local
321 bool lanes[4] = {true, false, true, false}; local
335 int16_t lanes[8] = {1, 2, 3, 4, 5, 6, 7, 8}; local
349 uint16_t lanes[8] = {1, 2, 3, 4, 5, 6, 7, 8}; local
363 bool lanes[8] = {true, false, true, false, true, false, true, false}; local
377 int8_t lanes[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; local
391 uint8_t lanes[16] = {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16}; local
405 bool lanes[16] = {true, false, true, false, true, false, true, false, local
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  /external/libhevc/common/arm/
ihevc_intra_pred_luma_dc.s 213 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
454 vdup.16 q12, d11[0] @3*dc + 2 (moved to all lanes)
  /external/mesa3d/src/gallium/drivers/nv50/codegen/
nv50_ir.cpp 573 lanes = 0xf;
737 i->lanes = lanes;
nv50_ir_emit_nv50.cpp 602 code[1] = 0x00200000 | (i->lanes << 14);
619 code[1] = 0x00200000 | (i->lanes << 14);
759 code[1] |= (i->lanes << 14);
    [all...]
nv50_ir_build_util.cpp 265 quadop->lanes = l;
nv50_ir.h 696 unsigned lanes : 4;
nv50_ir_peephole.cpp     [all...]
nv50_ir_lowering_nv50.cpp 628 // The lanes of a quad are grouped by the bit in the condition register they
750 // mov coordinates from lane l to all lanes
753 // add dPdx from lane l to lanes dx
756 // add dPdy from lane l to lanes dy
769 mov->lanes = 1 << l;
  /external/vixl/src/vixl/a64/
assembler-a64.h 203 // described. They do not consider the number of lanes that make up a vector.
206 // Check the number of lanes, ie. the format of the vector, using methods such
272 VRegister(unsigned code, unsigned size, unsigned lanes = 1)
273 : CPURegister(code, size, kVRegister), lanes_(lanes) {
312 // For consistency, we assert the number of lanes of these scalar registers,
333 int lanes() const {
    [all...]
assembler-a64.cc     [all...]
  /external/libvpx/libvpx/vpx_dsp/x86/
quantize_avx_x86_64.asm 61 pcmpeqw m4, m4 ; All word lanes -1
208 pcmpeqw m4, m4 ; All lanes -1
  /external/mesa3d/src/gallium/drivers/nvc0/codegen/
nv50_ir_emit_nvc0.cpp     [all...]
nv50_ir_lowering_nvc0.cpp 772 // mov coordinates from lane l to all lanes
775 // add dPdx from lane l to lanes dx
778 // add dPdy from lane l to lanes dy
791 mov->lanes = 1 << l;
    [all...]
  /external/v8/src/
factory.h 359 Handle<Type> New##Type(lane_type lanes[lane_count], \
factory.cc     [all...]
  /external/v8/src/heap/
heap.h     [all...]
heap.cc     [all...]
  /external/valgrind/none/tests/arm/
neon64.stdout.exp     [all...]
  /external/vixl/test/
test-disasm-a64.cc     [all...]

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