| /external/libvpx/libvpx/vpx_dsp/mips/ |
| idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
58 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4);
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7);
71 vec0 = reg0 + reg4;
72 reg0 = reg0 - reg4
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
359 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
439 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
[all...] |
| idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7,
24 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
31 DOTP_CONST_PAIR(reg0, reg8, cospi_16_64, cospi_16_64, reg0, reg8);
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14);
34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4,
59 loc0 = reg0 + loc1;
60 loc1 = reg0 - loc1
109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
[all...] |
| txfm_macros_msa.h | 16 #define DOTP_CONST_PAIR(reg0, reg1, cnst0, cnst1, out0, out1) { \
23 ILVRL_H2_SW((-reg1), reg0, s1_m, s0_m); \
24 ILVRL_H2_SW(reg0, reg1, s3_m, s2_m); \
|
| /external/v8/test/unittests/interpreter/ |
| bytecode-register-allocator-unittest.cc | 55 Register reg0 = temporaries.NextConsecutiveRegister(); local
62 CHECK(Register::AreContiguous(reg0, reg1, reg2, reg3));
|
| bytecode-array-builder-unittest.cc | 374 Register reg0(0);
383 CHECK_EQ(builder.RegisterIsParameterOrLocal(reg0), true);
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_fragshader.c | 48 GLuint reg0 = 0; local
76 reg0 |= (((index - GL_REG_0_ATI)*2) + 10 + useOddSrc) << (5*argPos);
79 reg0 |= (R200_TXC_ARG_A_TFACTOR_COLOR + useOddSrc) << (5*argPos);
84 reg0 |= (R200_TXC_ARG_A_TFACTOR1_COLOR + useOddSrc) << (5*argPos);
89 reg0 |= (R200_TXC_ARG_A_DIFFUSE_COLOR + useOddSrc) << (5*argPos);
92 reg0 |= (R200_TXC_ARG_A_SPECULAR_COLOR + useOddSrc) << (5*argPos);
96 reg0 |= R200_TXC_COMP_ARG_A << (4*argPos);
100 reg0 ^= R200_TXC_COMP_ARG_A << (4*argPos);
102 reg0 |= R200_TXC_BIAS_ARG_A << (4*argPos);
104 reg0 |= R200_TXC_SCALE_ARG_A << (4*argPos)
[all...] |
| /external/elfutils/tests/ |
| run-varlocs.sh | 71 [400524,400528) {reg0}
74 [40052e,400531) {reg0}
|
| /external/clang/test/OpenMP/ |
| threadprivate_messages.cpp | 101 // register int reg0 __asm__("0");
102 register int reg0 __asm__("esp"); // expected-note {{'reg0' defined here}}
103 #pragma omp threadprivate (reg0) // expected-error {{variable 'reg0' cannot be threadprivate because it is a global named register variable}}
|
| for_loop_messages.cpp | 17 // register int reg0 __asm__("0");
18 int reg0; variable
320 for (reg0 = 0; reg0 < 10; reg0 += 1)
321 c[reg0] = a[reg0];
|
| taskloop_loop_messages.cpp | 17 // register int reg0 __asm__("0");
18 int reg0; variable
321 for (reg0 = 0; reg0 < 10; reg0 += 1)
322 c[reg0] = a[reg0];
|
| taskloop_simd_loop_messages.cpp | 17 // register int reg0 __asm__("0");
18 int reg0; variable
322 for (reg0 = 0; reg0 < 10; reg0 += 1)
323 c[reg0] = a[reg0];
|
| /external/v8/test/cctest/ |
| test-utils-arm64.cc | 146 bool Equal64(const Register& reg0,
149 CHECK(reg0.Is64Bits() && reg1.Is64Bits());
150 int64_t expected = core->xreg(reg0.code());
|
| test-utils-arm64.h | 189 bool Equal64(const Register& reg0, const RegisterDump* core,
|
| /external/vixl/test/ |
| test-utils-a64.cc | 178 bool Equal64(const Register& reg0,
181 VIXL_ASSERT(reg0.Is64Bits() && reg1.Is64Bits());
182 int64_t expected = core->xreg(reg0.code());
|
| test-utils-a64.h | 209 bool Equal64(const Register& reg0, const RegisterDump* core,
|
| /external/v8/src/interpreter/ |
| bytecode-array-builder.cc | 375 BytecodeArrayBuilder& BytecodeArrayBuilder::ExchangeRegisters(Register reg0,
377 DCHECK(reg0 != reg1);
378 if (FitsInReg8Operand(reg0)) {
379 Output(Bytecode::kExchange, reg0.ToOperand(), reg1.ToWideOperand());
381 Output(Bytecode::kExchange, reg1.ToOperand(), reg0.ToWideOperand());
383 Output(Bytecode::kExchangeWide, reg0.ToWideOperand(), reg1.ToWideOperand());
1254 Register reg0 = local
[all...] |
| bytecode-array-builder.h | 101 BytecodeArrayBuilder& ExchangeRegisters(Register reg0, Register reg1);
|
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 489 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) {
495 xor_(reg0, reg0, scratch);
501 nor(scratch, reg0, zero_reg);
502 sll(at, reg0, 15);
503 addu(reg0, scratch, at);
506 srl(at, reg0, 12);
507 xor_(reg0, reg0, at);
510 sll(at, reg0, 2)
[all...] |
| /external/v8/src/mips64/ |
| macro-assembler-mips64.cc | 492 void MacroAssembler::GetNumberHash(Register reg0, Register scratch) {
498 xor_(reg0, reg0, scratch);
505 nor(scratch, reg0, zero_reg);
506 sll(at, reg0, 15);
507 addu(reg0, scratch, at);
510 srl(at, reg0, 12);
511 xor_(reg0, reg0, at);
514 sll(at, reg0, 2)
[all...] |
| /external/v8/src/x87/ |
| assembler-x87.h | 668 void cmp(Register reg0, Register reg1) { cmp(reg0, Operand(reg1)); }
753 void test(Register reg0, Register reg1) { test(reg0, Operand(reg1)); }
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_s390_helpers.c | 317 register ULong reg0 asm("0") = guest_state->guest_r0 & 0xF; /* r0[56:63] */
321 if (reg0 > S390_NUM_FACILITY_DW - 1)
322 reg0 = S390_NUM_FACILITY_DW - 1;
324 num_dw = reg0 + 1; /* number of double words written */
329 : "=m" (hoststfle), "+d"(reg0), "=d"(cc) : : "cc", "memory");
332 guest_state->guest_r0 = reg0;
[all...] |
| /art/compiler/utils/x86_64/ |
| assembler_x86_64.h | 512 void cmpl(CpuRegister reg0, CpuRegister reg1);
517 void cmpq(CpuRegister reg0, CpuRegister reg1);
518 void cmpq(CpuRegister reg0, const Immediate& imm);
519 void cmpq(CpuRegister reg0, const Address& address);
[all...] |
| /external/v8/src/compiler/ |
| bytecode-graph-builder.h | 267 void ExchangeRegisters(interpreter::Register reg0,
|
| /external/fio/ |
| configure | 1327 register unsigned long reg0 asm("0") = 0;
1333 : "=QS" (stfle_bits), "+d" (reg0)
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-opc.c | 2232 const int reg0 = first_reg; local
[all...] |
