| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| thumb1_unified.s | 21 rsbs r1, r2, #0 label
|
| thumb2_add.s | 31 rsbs r1, r6, #0
|
| armv1.s | 11 rsbs r0, r0, r0
|
| tcompat.d | 32 0+54 <[^>]*> e2709000 ? rsbs r9, r0, #0
|
| armv1.d | 18 0+1c <[^>]*> e0700000 ? rsbs r0, r0, r0
|
| thumb32.d | 182 0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0
183 0[0-9a-f]+ <[^>]+> ebd5 0500 rsbs r5, r5, r0
184 0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5
185 0[0-9a-f]+ <[^>]+> ebd0 0005 rsbs r0, r0, r5
186 0[0-9a-f]+ <[^>]+> ebd5 0000 rsbs r0, r5, r0
192 0[0-9a-f]+ <[^>]+> ebd0 0000 rsbs r0, r0, r0
680 0[0-9a-f]+ <[^>]+> f1d0 0000 rsbs r0, r0, #0
681 0[0-9a-f]+ <[^>]+> f1d0 0500 rsbs r5, r0, #0
682 0[0-9a-f]+ <[^>]+> f1d5 0000 rsbs r0, r5, #0
685 0[0-9a-f]+ <[^>]+> f1d9 0000 rsbs r0, r9, #
[all...] |
| thumb32.s | 154 arit3 rsb rsbs rsb.w rsbs.w
|
| /frameworks/av/media/libstagefright/codecs/avc/enc/src/ |
| sad_halfpel_inline.h | 55 rsbs tmp, tmp, tmp2, asr #1 ;
67 rsbs tmp, tmp2, tmp, asr #2 ;
80 "rsbs %1, %1, %2, asr #1\n\t"
93 "rsbs %1, %2, %1, asr #2\n\t"
|
| sad_inline.h | 178 rsbs tmp, tmp, tmp2 ;
320 RSBS x11, dmin, x10, lsr #16;
346 "rsbs %1, %1, %2\n\t"
|
| /frameworks/av/media/libstagefright/codecs/m4v_h263/enc/src/ |
| sad_halfpel_inline.h | 58 rsbs tmp, tmp, tmp2, asr #1 ;
70 rsbs tmp, tmp2, tmp, asr #2 ;
89 asm volatile("rsbs %1, %3, %4, asr #1\n\t"
109 asm volatile("rsbs %1, %4, %3, asr #2\n\t"
|
| sad_inline.h | 181 rsbs tmp, tmp, tmp2 ;
323 RSBS x11, dmin, x10, lsr #16;
354 asm volatile("rsbs %1, %4, %3\n\t"
|
| /external/valgrind/none/tests/arm/ |
| v6intThumb.stdout.exp | [all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 445 @ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42]
494 rsbs r1, r3, #0
496 @ CHECK: rsbs r1, r3, #0 @ encoding: [0x59,0x42]
|
| basic-arm-instructions.s | [all...] |
| diagnostics.s | 662 rsbs r7, r8, #-2149, #0
663 rsbs r7, r8, #100, #1
|
| basic-thumb2-instructions.s | [all...] |
| /art/compiler/utils/ |
| assembler_thumb_test.cc | 280 // The 16-bit RSBS Rd, Rn, #0, also known as NEGS Rd, Rn is specified using
282 __ rsbs(R0, R1, ShifterOperand(0));
283 __ rsbs(R0, R0, ShifterOperand(0)); // Check Rd == Rn code path.
299 __ rsbs(R0, R8, ShifterOperand(0)); // Check that this is not emitted as 16-bit.
300 __ rsbs(R8, R8, ShifterOperand(0)); // Check that this is not emitted as 16-bit (Rd == Rn).
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm32_test.cc | 807 TEST_F(AssemblerArm32Test, Rsbs) {
808 T4Helper(&arm::Arm32Assembler::rsbs, true, "rsb{cond}s {reg1}, {reg2}, {shift}", "rsbs");
|
| assembler_arm.h | 468 virtual void rsbs(Register rd, Register rn, const ShifterOperand& so, Condition cond = AL) { function in class:art::arm::ArmAssembler
[all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm.cc | [all...] |
| code_generator_arm.cc | [all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_arm.S | [all...] |
