| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| verbose-error.s | 13 urecpe v0.1d,v7.1d
|
| verbose-error.l | 24 [^:]*:13: Error: operand mismatch -- `urecpe v0.1d,v7.1d'
26 [^:]*:13: Info: urecpe v0.2s,v7.2s
28 [^:]*:13: Info: urecpe v0.4s,v7.4s
|
| illegal.s | 23 // For urecpe and ursqrte, only 2s and 4s are accepted qualifiers.
24 urecpe v0.1d, v7.1d
25 urecpe v0.2d, v7.2d
|
| illegal.l | 2 [^:]*:24: Error: .*`urecpe v0.1d,v7.1d'
3 [^:]*:25: Error: .*`urecpe v0.2d,v7.2d'
|
| /external/llvm/test/MC/AArch64/ |
| neon-simd-misc.s | 670 urecpe v6.4s, v8.4s
671 urecpe v4.2s, v0.2s
673 // CHECK: urecpe v6.4s, v8.4s // encoding: [0x06,0xc9,0xa1,0x4e]
674 // CHECK: urecpe v4.2s, v0.2s // encoding: [0x04,0xc8,0xa1,0x0e]
[all...] |
| neon-diagnostics.s | [all...] |
| arm64-advsimd.s | 604 urecpe.2s v0, v0
654 ; CHECK: urecpe.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x0e]
[all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | [all...] |
| logic-a64.cc | 4773 LogicVRegister Simulator::urecpe(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| /external/vixl/test/ |
| test-simulator-a64.cc | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.stdout.exp | [all...] |
