| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| verbose-error.s | 20 ursqrte v2.8b, v3.8b
|
| verbose-error.l | 56 [^:]*:20: Error: operand mismatch -- `ursqrte v2.8b,v3.8b'
58 [^:]*:20: Info: ursqrte v2.2s,v3.2s
60 [^:]*:20: Info: ursqrte v2.4s,v3.4s
|
| illegal.s | 23 // For urecpe and ursqrte, only 2s and 4s are accepted qualifiers.
26 ursqrte v0.1d, v7.1d
27 ursqrte v0.2d, v7.2d
|
| illegal.l | 4 [^:]*:26: Error: .*`ursqrte v0.1d,v7.1d'
5 [^:]*:27: Error: .*`ursqrte v0.2d,v7.2d'
|
| /external/llvm/test/MC/AArch64/ |
| neon-simd-misc.s | 676 ursqrte v6.4s, v8.4s
677 ursqrte v4.2s, v0.2s
679 // CHECK: ursqrte v6.4s, v8.4s // encoding: [0x06,0xc9,0xa1,0x6e]
680 // CHECK: ursqrte v4.2s, v0.2s // encoding: [0x04,0xc8,0xa1,0x2e]
[all...] |
| neon-diagnostics.s | [all...] |
| arm64-advsimd.s | 605 ursqrte.2s v0, v0
655 ; CHECK: ursqrte.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x2e]
[all...] |
| /external/vixl/src/vixl/a64/ |
| simulator-a64.h | [all...] |
| assembler-a64.h | [all...] |
| macro-assembler-a64.h | [all...] |
| simulator-a64.cc | [all...] |
| assembler-a64.cc | [all...] |
| logic-a64.cc | 4740 LogicVRegister Simulator::ursqrte(VectorFormat vform, function in class:vixl::Simulator
[all...] |
| /external/vixl/test/ |
| test-simulator-a64.cc | [all...] |
| /external/valgrind/none/tests/arm64/ |
| fp_and_simd.stdout.exp | [all...] |
