| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 81 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
82 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 },
110 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
111 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
135 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
136 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
142 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
143 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
145 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
146 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| ARMISelLowering.cpp | 154 addTypeForNEON(VT, MVT::f64, MVT::v2i32);
470 addDRTypeForNEON(MVT::v2i32);
580 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom);
588 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom);
598 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom);
632 MVT::v2i32}) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 88 v2i32 = 39, // 2 x i32 enumerator in enum:llvm::MVT::SimpleValueType
235 SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 ||
336 case v2i32:
407 case v2i32:
466 case v2i32:
618 if (NumElements == 2) return MVT::v2i32;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
218 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 },
249 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
252 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 },
256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 },
259 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
263 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext).
277 // Complex, from v2f64: legal type is v2i32, 1 narrowing => ~2.
278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 },
281 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f64, 2 }
[all...] |
| AArch64ISelDAGToDAG.cpp | 488 case MVT::v2i32:
[all...] |
| AArch64ISelLowering.cpp | 94 addDRTypeForNEON(MVT::v2i32);
429 // load, floating-point truncating stores, or v2i32->v2i16 truncating store.
577 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom);
578 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom);
594 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand);
634 AddPromotedToType(ISD::LOAD, VT.getSimpleVT(), MVT::v2i32);
637 AddPromotedToType(ISD::STORE, VT.getSimpleVT(), MVT::v2i32);
717 addTypeForNEON(VT, MVT::v2i32);
[all...] |
| /external/clang/test/CodeGen/ |
| systemz-abi-vector.c | 22 typedef __attribute__((vector_size(8))) int v2i32; typedef
86 v2i32 pass_v2i32(v2i32 arg) { return arg; }
[all...] |
| x86_64-arguments.c | 290 typedef unsigned v2i32 __attribute((__vector_size__(8))); typedef
291 v2i32 f36(v2i32 arg) { return arg; }
|
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 237 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
241 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32,
270 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32,
284 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
|
| SparcISelLowering.cpp | 237 assert(VA.getLocVT() == MVT::v2i32);
238 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would
424 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32);
476 assert(VA.getValVT() == MVT::f64 || MVT::v2i32);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 64 (int)MVT::v2i32,
92 (int)MVT::v2i32,
501 INTTY = MVT::v2i32;
649 INTTY = MVT::v2i32;
667 INTTY = MVT::v2i32;
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 166 case MVT::v2i32: return "v2i32";
244 case MVT::v2i32: return VectorType::get(Type::getInt32Ty(Context), 2);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 242 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
406 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) {
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 52 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
172 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand);
198 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
490 return MVT::v2i32;
[all...] |
| AMDGPUISelLowering.cpp | 114 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
135 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
136 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
154 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32);
176 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
292 MVT::v2i32, MVT::v4i32
[all...] |
| R600ISelLowering.cpp | 41 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass);
68 setOperationAction(ISD::SETCC, MVT::v2i32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v2i32, Expand);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expand);
128 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
149 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
158 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i32, Custom);
163 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i32, Custom);
[all...] |
| AMDGPUISelDAGToDAG.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 99 case MVT::v2i32: return "MVT::v2i32";
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 433 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64.
599 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 },
604 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86InstComments.cpp | 434 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelLowering.cpp | 67 case MVT::v2i32:
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 646 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.cpp | [all...] |
