| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| crc32.s | 24 crc32b w3, w7, w15
25 crc32h w7, w15, w3
26 crc32w w15, w3, w7
27 crc32x w3, w7, x15
28 crc32cb w3, w7, w15
29 crc32ch w7, w15, w3
30 crc32cw w15, w3, w7
31 crc32cx w3, w7, x15
|
| crc32.d | 9 0: 1acf40e3 crc32b w3, w7, w15
10 4: 1ac345e7 crc32h w7, w15, w3
11 8: 1ac7486f crc32w w15, w3, w7
12 c: 9acf4ce3 crc32x w3, w7, x15
13 10: 1acf50e3 crc32cb w3, w7, w15
14 14: 1ac355e7 crc32ch w7, w15, w3
15 18: 1ac7586f crc32cw w15, w3, w7
16 1c: 9acf5ce3 crc32cx w3, w7, x15
|
| bitfield-no-aliases.d | 9 0: 13001cff sbfm wzr, w7, #0, #7
11 8: 13003cff sbfm wzr, w7, #0, #15
14 14: 53001cff ubfm wzr, w7, #0, #7
15 18: 53001cff ubfm wzr, w7, #0, #7
16 1c: 53003cff ubfm wzr, w7, #0, #15
17 20: 53003cff ubfm wzr, w7, #0, #15
18 24: 2a0703ff orr wzr, wzr, w7
19 28: 2a0703ff orr wzr, wzr, w7
20 2c: 13007cff sbfm wzr, w7, #0, #31
21 30: 13107cff sbfm wzr, w7, #16, #3
[all...] |
| ldst-reg-imm-post-ind.d | 98 168: 381007e7 strb w7, \[sp\],#-256
99 16c: 381557e7 strb w7, \[sp\],#-171
100 170: 380007e7 strb w7, \[sp\],#0
101 174: 380027e7 strb w7, \[sp\],#2
102 178: 380047e7 strb w7, \[sp\],#4
103 17c: 380087e7 strb w7, \[sp\],#8
104 180: 380107e7 strb w7, \[sp\],#16
105 184: 380557e7 strb w7, \[sp\],#85
106 188: 380ff7e7 strb w7, \[sp\],#255
107 18c: 781007e7 strh w7, \[sp\],#-25
[all...] |
| ldst-reg-imm-pre-ind.d | 98 168: 38100fe7 strb w7, \[sp,#-256\]!
99 16c: 38155fe7 strb w7, \[sp,#-171\]!
100 170: 38000fe7 strb w7, \[sp,#0\]!
101 174: 38002fe7 strb w7, \[sp,#2\]!
102 178: 38004fe7 strb w7, \[sp,#4\]!
103 17c: 38008fe7 strb w7, \[sp,#8\]!
104 180: 38010fe7 strb w7, \[sp,#16\]!
105 184: 38055fe7 strb w7, \[sp,#85\]!
106 188: 380fffe7 strb w7, \[sp,#255\]!
107 18c: 78100fe7 strh w7, \[sp,#-256\]
[all...] |
| fp_cvt_int.d | 8 0: 1e2000e7 fcvtns w7, s7
10 8: 1e2100e7 fcvtnu w7, s7
12 10: 1e2800e7 fcvtps w7, s7
14 18: 1e2900e7 fcvtpu w7, s7
16 20: 1e3000e7 fcvtms w7, s7
18 28: 1e3100e7 fcvtmu w7, s7
20 30: 1e3800e7 fcvtzs w7, s7
22 38: 1e3900e7 fcvtzu w7, s7
24 40: 1e2200e7 scvtf s7, w7
26 48: 1e2300e7 ucvtf s7, w7
[all...] |
| ldst-reg-uns-imm.d | 118 1b8: 381003e7 sturb w7, \[sp,#-256\]
119 1bc: 381553e7 sturb w7, \[sp,#-171\]
120 1c0: 390003e7 strb w7, \[sp\]
121 1c4: 390003e7 strb w7, \[sp\]
122 1c8: 39000be7 strb w7, \[sp,#2\]
123 1cc: 390013e7 strb w7, \[sp,#4\]
124 1d0: 390023e7 strb w7, \[sp,#8\]
125 1d4: 390043e7 strb w7, \[sp,#16\]
126 1d8: 390157e7 strb w7, \[sp,#85\]
127 1dc: 3903ffe7 strb w7, \[sp,#255\
[all...] |
| ldst-reg-reg-offset.d | 8 0: 3c274be7 str b7, \[sp,w7,uxtw\]
9 4: 3c275be7 str b7, \[sp,w7,uxtw #0\]
10 8: 7c274be7 str h7, \[sp,w7,uxtw\]
11 c: 7c275be7 str h7, \[sp,w7,uxtw #1\]
12 10: bc274be7 str s7, \[sp,w7,uxtw\]
13 14: bc275be7 str s7, \[sp,w7,uxtw #2\]
14 18: fc274be7 str d7, \[sp,w7,uxtw\]
15 1c: fc275be7 str d7, \[sp,w7,uxtw #3\]
16 20: 3ca74be7 str q7, \[sp,w7,uxtw\]
17 24: 3ca75be7 str q7, \[sp,w7,uxtw #4\
[all...] |
| ldst-reg-unscaled-imm.d | 108 190: 381003e7 sturb w7, \[sp,#-256\]
109 194: 381553e7 sturb w7, \[sp,#-171\]
110 198: 380003e7 sturb w7, \[sp\]
111 19c: 380003e7 sturb w7, \[sp\]
112 1a0: 380023e7 sturb w7, \[sp,#2\]
113 1a4: 380043e7 sturb w7, \[sp,#4\]
114 1a8: 380083e7 sturb w7, \[sp,#8\]
115 1ac: 380103e7 sturb w7, \[sp,#16\]
116 1b0: 380553e7 sturb w7, \[sp,#85\]
117 1b4: 380ff3e7 sturb w7, \[sp,#255\
[all...] |
| mov.s | 13 mov wsp, w7
19 mov w7, w15
31 mov w7, v15.s[3]
|
| addsub.d | 8 0: 0b0100f0 add w16, w7, w1
9 4: 0b2100f0 add w16, w7, w1, uxtb
10 8: 0b2100f0 add w16, w7, w1, uxtb
11 c: 0b2104f0 add w16, w7, w1, uxtb #1
12 10: 0b2108f0 add w16, w7, w1, uxtb #2
13 14: 0b210cf0 add w16, w7, w1, uxtb #3
14 18: 0b2110f0 add w16, w7, w1, uxtb #4
15 1c: 0b2120f0 add w16, w7, w1, uxth
16 20: 0b2120f0 add w16, w7, w1, uxth
17 24: 0b2124f0 add w16, w7, w1, uxth #
[all...] |
| ldst-reg-pair.d | 8 0: 29203fe7 stp w7, w15, \[sp,#-256\]
9 4: 2930bfe7 stp w7, w15, \[sp,#-124\]
10 8: 293fbfe7 stp w7, w15, \[sp,#-4\]
11 c: 29003fe7 stp w7, w15, \[sp\]
12 10: 2907bfe7 stp w7, w15, \[sp,#60\]
13 14: 291fbfe7 stp w7, w15, \[sp,#252\]
14 18: 29603fe7 ldp w7, w15, \[sp,#-256\]
15 1c: 2970bfe7 ldp w7, w15, \[sp,#-124\]
16 20: 297fbfe7 ldp w7, w15, \[sp,#-4\]
17 24: 29403fe7 ldp w7, w15, \[sp\
[all...] |
| mov-no-aliases.d | 11 8: 110000ff add wsp, w7, #0x0
16 1c: 2a0f03e7 orr w7, wzr, w15
24 3c: 0e1c3de7 umov w7, v15\.s\[3\]
|
| mov.d | 10 8: 110000ff mov wsp, w7
15 1c: 2a0f03e7 mov w7, w15
23 3c: 0e1c3de7 mov w7, v15\.s\[3\]
|
| bitfield-alias.s | 33 \op wzr, w7
38 \op xzr, w7
43 \op wzr, w7, \shift
53 \op wzr, w7, #\lsb, #\width
|
| /art/runtime/interpreter/mterp/arm64/ |
| op_return.S | 9 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
11 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
|
| op_return_void.S | 3 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
5 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
|
| op_return_void_no_barrier.S | 1 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
3 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
|
| op_return_wide.S | 8 ldr w7, [xSELF, #THREAD_FLAGS_OFFSET]
10 ands w7, w7, #(THREAD_SUSPEND_REQUEST | THREAD_CHECKPOINT_REQUEST)
|
| /external/llvm/test/MC/AArch64/ |
| arm64-basic-a64-instructions.s | 3 crc32b w5, w7, w20
6 crc32x w7, w9, x20
11 // CHECK: crc32b w5, w7, w20 // encoding: [0xe5,0x40,0xd4,0x1a]
14 // CHECK: crc32x w7, w9, x20 // encoding: [0x27,0x4d,0xd4,0x9a]
|
| arm64-diagno-predicate.s | 20 crc32b w5, w7, w20
22 // CHECK-ERROR-NEXT: crc32b w5, w7, w20
|
| /system/core/libpixelflinger/arch-arm64/ |
| col32cb16blend.S | 68 and w7, w9, w8, lsr #5 // extract dest green
72 madd w7, w7, w5, w12 // dest green * alpha + src green
76 lsr w7, w7, #8 // shift down green
78 orr w6, w6, w7, lsl #5 // shift green into 565
|
| /external/llvm/test/MC/Mips/msa/ |
| test_vec.s | 4 # CHECK: bmnz.v $w17, $w6, $w7 # encoding: [0x78,0x87,0x34,0x5e]
7 # CHECK: nor.v $w7, $w31, $w0 # encoding: [0x78,0x40,0xf9,0xde]
9 # CHECK: xor.v $w7, $w27, $w15 # encoding: [0x78,0x6f,0xd9,0xde]
12 bmnz.v $w17, $w6, $w7
15 nor.v $w7, $w31, $w0
17 xor.v $w7, $w27, $w15
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
| erratum843419.s | 10 str w7, [sp,12]
22 str w7, [sp,12]
32 ldr w7, [sp,12]
33 add w0, w7, w7
44 ldr w7, [x4,8]!
|
| emit-relocs-285.s | 7 ldr w7, [x3, #:lo12:tempy2]
|
