| /external/llvm/lib/Transforms/Scalar/ |
| LoopDistribute.cpp | 160 for (auto &Inst : *Block)
161 if (!Set.count(&Inst)) {
162 Instruction *NewInst = &Inst;
173 for (auto *Inst : make_range(Unused.rbegin(), Unused.rend())) {
174 if (!Inst->use_empty())
175 Inst->replaceAllUsesWith(UndefValue::get(Inst->getType()));
176 Inst->eraseFromParent();
229 /// \brief Adds \p Inst into the current partition if that is marked to
231 void addToCyclicPartition(Instruction *Inst) {
[all...] |
| PlaceSafepoints.cpp | 379 Instruction *Inst = CS.getInstruction();
380 if (IntrinsicInst *II = dyn_cast<IntrinsicInst>(Inst)) {
461 Instruction *inst = &I; local
462 if (isa<CallInst>(inst) || isa<InvokeInst>(inst)) {
463 CallSite CS(inst);
[all...] |
| LoopIdiomRecognize.cpp | 364 Instruction *Inst = &*I++;
366 if (MemSetInst *MSI = dyn_cast<MemSetInst>(Inst)) {
837 Instruction *Inst = &*Iter;
838 if (Inst->getOpcode() != Instruction::Add)
841 ConstantInt *Inc = dyn_cast<ConstantInt>(Inst->getOperand(1));
845 PHINode *Phi = dyn_cast<PHINode>(Inst->getOperand(0));
[all...] |
| SCCP.cpp | 457 if (BBExecutable.count(I->getParent())) // Inst is executable?
[all...] |
| /external/llvm/lib/Transforms/Utils/ |
| PromoteMemoryToRegister.cpp | 319 Instruction *Inst = cast<Instruction>(*UUI);
321 Inst->eraseFromParent();
[all...] |
| /external/llvm/utils/TableGen/ |
| DAGISelMatcherGen.cpp | 665 GetInstPatternNode(const DAGInstruction &Inst, const TreePatternNode *N) {
666 const TreePattern *InstPat = Inst.getPattern();
719 const DAGInstruction &Inst = CGP.getInstruction(Op);
727 const TreePatternNode *InstPatNode = GetInstPatternNode(Inst, N);
756 unsigned NumResults = Inst.getNumResults();
[all...] |
| AsmWriterEmitter.cpp | 57 assert(I != CGIAWIMap.end() && "Didn't find inst!");
158 const AsmWriterInst *Inst = getAsmWriterInstByID(i);
159 if (!Inst)
163 if (Inst->Operands.empty())
166 Command = " " + Inst->Operands[0].getCode() + "\n";
175 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
182 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
381 if (AsmWriterInst *Inst = getAsmWriterInstByID(i))
382 if (!Inst->Operands.empty()) {
384 assert(NumOps <= Inst->Operands.size() &
[all...] |
| /external/regex-re2/re2/ |
| prog.h | 49 // Opcodes for Inst
84 class Inst {
86 Inst() : out_opcode_(0), out1_(0) { }
110 return p->inst(out())->opcode() == kInstByteRange;
113 // Does this inst (an kInstByteRange) match c?
170 DISALLOW_EVIL_CONSTRUCTORS(Inst);
198 Inst *inst(int id) { return &inst_[id]; } function in class:re2::Prog
355 Inst* inst_; // pointer to instruction array
|
| /external/clang/lib/CodeGen/ |
| CGExprAgg.cpp | [all...] |
| CGAtomic.cpp | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCAssembler.h | 265 /// Inst - The instruction this is a fragment for.
266 MCInst Inst;
272 MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI,
275 Inst(Inst), STI(STI) {}
277 const MCInst &getInst() const { return Inst; }
278 void setInst(const MCInst &Value) { Inst = Value; }
|
| /external/llvm/lib/Analysis/ |
| BasicAliasAnalysis.cpp | 635 if (const Instruction *inst = dyn_cast<Instruction>(V))
636 return inst->getParent()->getParent();
[all...] |
| /external/llvm/lib/CodeGen/ |
| PeepholeOptimizer.cpp | 221 const MachineInstr *Inst;
224 ValueTrackerResult() : Inst(nullptr) {}
225 ValueTrackerResult(unsigned Reg, unsigned SubReg) : Inst(nullptr) {
231 void setInst(const MachineInstr *I) { Inst = I; }
232 const MachineInstr *getInst() const { return Inst; }
236 Inst = nullptr;
[all...] |
| /external/llvm/lib/MC/ |
| MCStreamer.cpp | 226 for (const MCCFIInstruction& Inst : MAI->getInitialFrameState()) {
227 if (Inst.getOperation() == MCCFIInstruction::OpDefCfa ||
228 Inst.getOperation() == MCCFIInstruction::OpDefCfaRegister) {
229 Frame.CurrentCfaRegister = Inst.getRegister();
484 WinEH::Instruction Inst = Win64EH::Instruction::PushNonVol(Label, Register);
485 CurrentWinFrameInfo->Instructions.push_back(Inst);
500 WinEH::Instruction Inst =
503 CurrentWinFrameInfo->Instructions.push_back(Inst);
516 WinEH::Instruction Inst = Win64EH::Instruction::Alloc(Label, Size);
517 CurrentWinFrameInfo->Instructions.push_back(Inst);
[all...] |
| /external/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 87 void expandSET(MCInst &Inst, SMLoc IDLoc,
281 void addRegOperands(MCInst &Inst, unsigned N) const {
283 Inst.addOperand(MCOperand::createReg(getReg()));
286 void addImmOperands(MCInst &Inst, unsigned N) const {
289 addExpr(Inst, Expr);
292 void addExpr(MCInst &Inst, const MCExpr *Expr) const{
295 Inst.addOperand(MCOperand::createImm(0));
297 Inst.addOperand(MCOperand::createImm(CE->getValue()));
299 Inst.addOperand(MCOperand::createExpr(Expr));
302 void addMEMrrOperands(MCInst &Inst, unsigned N) const
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_pair_schedule.c | 123 struct rc_instruciont * Inst;
198 struct schedule_instruction * inst)
204 if (list_ptr == inst) {
206 prev->NextReady = inst->NextReady;
208 *list = inst->NextReady;
210 inst->NextReady = NULL;
216 static void add_inst_to_list(struct schedule_instruction ** list, struct schedule_instruction * inst)
218 inst->NextReady = *list;
219 *list = inst;
223 struct schedule_instruction * inst)
1326 struct rc_instruction * inst = c->Base.Program.Instructions.Next; local
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/rsc.io/arm/armasm/ |
| inst.go | 46 // An Inst is a single instruction.
47 type Inst struct {
54 func (i Inst) String() string {
|
| /prebuilts/go/linux-x86/src/cmd/internal/rsc.io/arm/armasm/ |
| inst.go | 46 // An Inst is a single instruction.
47 type Inst struct {
54 func (i Inst) String() string {
|
| /external/clang/lib/Sema/ |
| SemaTemplateInstantiate.cpp | 218 ActiveTemplateInstantiation Inst;
219 Inst.Kind = Kind;
220 Inst.PointOfInstantiation = PointOfInstantiation;
221 Inst.Entity = Entity;
222 Inst.Template = Template;
223 Inst.TemplateArgs = TemplateArgs.data();
224 Inst.NumTemplateArgs = TemplateArgs.size();
225 Inst.DeductionInfo = DeductionInfo;
226 Inst.InstantiationRange = InstantiationRange;
228 SemaRef.ActiveTemplateInstantiations.push_back(Inst);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGISel.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| AMDGPUAsmParser.cpp | 99 void addImmOperands(MCInst &Inst, unsigned N) const {
100 Inst.addOperand(MCOperand::createImm(getImm()));
107 void addRegOperands(MCInst &Inst, unsigned N) const {
108 Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), *Reg.STI)));
111 void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
113 addRegOperands(Inst, N);
115 addImmOperands(Inst, N);
118 void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
119 Inst.addOperand(MCOperand::createImm(
121 addRegOperands(Inst, N)
[all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 60 void addSubinstOperands(MCInst *MI, unsigned opcode, unsigned inst) const;
67 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,
70 static DecodeStatus DecodeIntRegsLow8RegisterClass(MCInst &Inst, unsigned RegNo,
73 static DecodeStatus DecodeVectorRegsRegisterClass(MCInst &Inst, unsigned RegNo,
76 static DecodeStatus DecodeDoubleRegsRegisterClass(MCInst &Inst, unsigned RegNo,
79 static DecodeStatus DecodeVecDblRegsRegisterClass(MCInst &Inst, unsigned RegNo,
82 static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
85 static DecodeStatus DecodeVecPredRegsRegisterClass(MCInst &Inst, unsigned RegNo,
88 static DecodeStatus DecodeCtrRegsRegisterClass(MCInst &Inst, unsigned RegNo,
91 static DecodeStatus DecodeModRegsRegisterClass(MCInst &Inst, unsigned RegNo
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXAsmPrinter.cpp | 164 MCInst Inst;
165 lowerToMCInst(MI, Inst);
166 EmitToStreamer(*OutStreamer, Inst);
[all...] |
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 281 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
538 void addRegOperands(MCInst &Inst, unsigned N) const {
542 void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
544 Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
547 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
549 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
552 void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
554 Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
557 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
559 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]))
[all...] |
