| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 237 MachineBasicBlock *MBB = mf.CreateMachineBasicBlock(&*BB);
238 MBBMap[&*BB] = MBB;
239 MF->push_back(MBB);
245 MBB->setHasAddressTaken();
268 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
552 MachineBasicBlock *MBB) {
558 MMI.addCleanup(MBB);
566 MMI.addCatchTypeInfo(MBB,
576 MMI.addFilterTypeInfo(MBB, FilterList);
|
| SelectionDAGBuilder.h | 153 MachineBasicBlock *MBB;
160 MachineBasicBlock *MBB, BranchProbability Prob) {
165 C.MBB = MBB;
248 MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
255 /// MBB - the MBB into which to emit the code for the indirect jump.
256 MachineBasicBlock *MBB;
257 /// Default - the MBB of the default bb, which is a successor of the range
258 /// check MBB. This is when updating PHI nodes in successors
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ConditionalCompares.cpp | 182 /// Find the compare instruction in MBB that controls the conditional branch.
184 MachineInstr *findConvertibleCompare(MachineBasicBlock *MBB);
186 /// Return true if all non-terminator instructions in MBB can be safely
188 bool canSpeculateInstrs(MachineBasicBlock *MBB, const MachineInstr *CmpMI);
199 /// If the sub-CFG headed by MBB can be cmp-converted, initialize the
201 bool canConvert(MachineBasicBlock *MBB);
220 // PHI operands come in (VReg, MBB) pairs.
222 MachineBasicBlock *MBB = I.getOperand(oi + 1).getMBB();
224 if (MBB == Head) {
228 if (MBB == CmpBB)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 69 unsigned createDupLane(MachineBasicBlock &MBB,
75 unsigned createExtractSubreg(MachineBasicBlock &MBB,
81 unsigned createVExt(MachineBasicBlock &MBB,
86 unsigned createRegSequence(MachineBasicBlock &MBB,
91 unsigned createInsertSubreg(MachineBasicBlock &MBB,
96 unsigned createImplicitDef(MachineBasicBlock &MBB,
430 A15SDOptimizer::createDupLane(MachineBasicBlock &MBB,
436 AddDefaultPred(BuildMI(MBB,
449 A15SDOptimizer::createExtractSubreg(MachineBasicBlock &MBB,
455 BuildMI(MBB,
[all...] |
| ARMBaseRegisterInfo.cpp | 381 emitLoadConstPool(MachineBasicBlock &MBB,
387 MachineFunction &MF = *MBB.getParent();
394 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
557 materializeFrameBaseRegister(MachineBasicBlock *MBB,
560 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
564 MachineBasicBlock::iterator Ins = MBB->begin();
566 if (Ins != MBB->end())
569 const MachineFunction &MF = *MBB->getParent();
570 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
575 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
128 BuildMI(MBB, I, DL, get(Mips::WRDSP))
167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
180 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
185 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
226 const Function *Func = MBB.getParent()->getFunction();
229 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
232 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
235 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 324 MachineBasicBlock &MBB = *MI.getParent();
326 MachineFunction &MF = *MBB.getParent();
359 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
363 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
367 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
384 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
389 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
395 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
399 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
409 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg
[all...] |
| PPCVSXSwapRemoval.cpp | 245 for (MachineBasicBlock &MBB : *MF) {
246 for (MachineInstr &MI : MBB) {
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SlotIndexes.h | 351 /// MBBRanges - Map MBB number to (start, stop) indexes.
355 /// and MBB id.
396 void repairIndexesInRange(MachineBasicBlock *MBB,
447 const MachineBasicBlock *MBB = MI->getParent();
448 assert(MBB && "MI must be inserted inna basic block");
449 MachineBasicBlock::const_iterator I = MI, B = MBB->begin();
452 return getMBBStartIdx(MBB);
464 const MachineBasicBlock *MBB = MI->getParent();
465 assert(MBB && "MI must be inserted inna basic block");
466 MachineBasicBlock::const_iterator I = MI, E = MBB->end()
[all...] |
| MachineBasicBlock.h | 457 /// one. This is usually done when the current update on this MBB is done, and
460 /// MBB::removeSuccessor() has an option to do this automatically.
487 /// Transfers all the successors from MBB to this machine basic block (i.e.,
499 /// Return true if the specified MBB is a predecessor of this block.
500 bool isPredecessor(const MachineBasicBlock *MBB) const;
502 /// Return true if the specified MBB is a successor of this block.
503 bool isSuccessor(const MachineBasicBlock *MBB) const;
505 /// Return true if the specified MBB will be emitted immediately after this
507 /// transfer to the specified MBB. Note that MBB need not be a successor a
[all...] |
| /external/llvm/lib/CodeGen/ |
| EarlyIfConversion.cpp | 140 /// Return true if all non-terminator instructions in MBB can be safely
142 bool canSpeculateInstrs(MachineBasicBlock *MBB);
165 /// canConvertIf - If the sub-CFG headed by MBB can be if-converted,
167 bool canConvertIf(MachineBasicBlock *MBB);
176 /// canSpeculateInstrs - Returns true if all the instructions in MBB can safely
184 bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
187 if (!MBB->livein_empty()) {
188 DEBUG(dbgs() << "BB#" << MBB->getNumber() << " has live-ins.\n");
196 for (MachineBasicBlock::iterator I = MBB->begin(),
197 E = MBB->getFirstTerminator(); I != E; ++I)
[all...] |
| RegAllocFast.cpp | 63 MachineBasicBlock *MBB;
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
308 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::DBG_VALUE))
313 assert(NewDV->getParent() == MBB && "dangling parent pointer");
637 TII->loadRegFromStackSlot(*MBB, MI, LRI->PhysReg, FrameIndex, RC, TRI);
794 DEBUG(dbgs() << "\nAllocating " << *MBB);
799 MachineBasicBlock::iterator MII = MBB->begin();
802 for (const auto &LI : MBB->liveins())
809 // Otherwise, sequentially allocate each instruction in the MBB.
810 while (MII != MBB->end())
[all...] |
| SplitKit.cpp | 58 const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
60 const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
62 SlotIndex MBBEnd = LIS.getMBBEndIdx(MBB);
67 MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
68 if (FirstTerm == MBB->end())
78 for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin();
93 // Find the value leaving MBB.
98 // If the value leaving MBB was defined after the call in MBB, it can'
[all...] |
| TailDuplication.cpp | 120 bool TailDuplicateAndUpdate(MachineBasicBlock *MBB,
124 void RemoveDeadBlock(MachineBasicBlock *MBB);
164 MachineBasicBlock *MBB = &*I;
165 SmallSetVector<MachineBasicBlock*, 8> Preds(MBB->pred_begin(),
166 MBB->pred_end());
167 MachineBasicBlock::iterator MI = MBB->begin();
168 while (MI != MBB->end()) {
183 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI;
193 dbgs() << "Warning: malformed PHI in BB#" << MBB->getNumber()
200 dbgs() << "Malformed PHI in BB#" << MBB->getNumber() << ": " << *MI
[all...] |
| BranchFolding.cpp | 11 // directly to the target block. This pass often results in dead MBB's, which
123 void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) {
124 assert(MBB->pred_empty() && "MBB must be dead!");
125 DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
127 MachineFunction *MF = MBB->getParent();
129 while (!MBB->succ_empty())
130 MBB->removeSuccessor(MBB->succ_end()-1)
[all...] |
| InlineSpiller.cpp | 415 // This is an alternative def earlier in the same MBB.
735 MachineBasicBlock *MBB = LIS.getMBBFromIndex(SVI.SpillVNI->def);
738 MII = MBB->SkipPHIsAndLabels(MBB->begin());
746 TII.storeRegToStackSlot(*MBB, MII, SVI.SpillReg, false, StackSlot,
833 MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
834 for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
835 PE = MBB->pred_end(); PI != PE; ++PI) {
[all...] |
| LiveDebugVariables.cpp | 91 bool dominates(MachineBasicBlock *MBB) {
94 return LBlocks.count(MBB) != 0 || LS.dominates(DL, MBB);
131 /// insertDebugValue - Insert a DBG_VALUE into MBB at Idx for LocNo.
132 void insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, unsigned LocNo,
513 MachineBasicBlock *MBB = &*MFI;
514 for (MachineBasicBlock::iterator MBBI = MBB->begin(), MBBE = MBB->end();
521 SlotIndex Idx = MBBI == MBB->begin() ?
522 LIS->getMBBStartIdx(MBB)
[all...] |
| LiveIntervalAnalysis.cpp | 225 for (MachineBasicBlock &MBB : *MF) {
226 std::pair<unsigned, unsigned> &RMB = RegMaskBlocks[MBB.getNumber()];
230 if (const uint32_t *Mask = MBB.getBeginClobberMask(TRI)) {
231 RegMaskSlots.push_back(Indexes->getMBBStartIdx(&MBB));
235 for (MachineInstr &MI : MBB) {
245 if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
246 RegMaskSlots.push_back(Indexes->getMBBEndIdx(&MBB));
317 const MachineBasicBlock *MBB = &*MFI;
320 if ((MFI != MF->begin() && !MBB->isEHPad()) || MBB->livein_empty()
[all...] |
| MachineBasicBlock.cpp | 56 assert(getNumber() >= 0 && "cannot get label for unreachable MBB");
66 raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
67 MBB.print(OS);
71 /// When an MBB is added to an MF, we need to update the parent pointer of the
72 /// MBB, the MBB numbering, and any instructions in the MBB to be on the right
75 /// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
76 /// gets the next available unique MBB number. If it is removed from a
118 /// When moving a range of instructions from one MBB list to another, we need t
[all...] |
| MachineInstr.cpp | 63 if (MachineBasicBlock *MBB = MI->getParent())
64 if (MachineFunction *MF = MBB->getParent()) {
105 if (MachineBasicBlock *MBB = MI->getParent())
106 if (MachineFunction *MF = MBB->getParent()) {
123 if (MachineBasicBlock *MBB = MI->getParent()) {
124 if (MachineFunction *MF = MBB->getParent())
181 if (MachineBasicBlock *MBB = MI->getParent())
182 if (MachineFunction *MF = MBB->getParent())
688 if (MachineBasicBlock *MBB = getParent())
689 return &MBB->getParent()->getRegInfo()
[all...] |
| MachineLICM.cpp | 94 bool isExitBlock(const MachineBasicBlock *MBB) const {
95 return std::find(ExitBlocks.begin(), ExitBlocks.end(), MBB) !=
119 // If a MBB does not dominate loop exiting blocks then it may not safe
195 void EnterScope(MachineBasicBlock *MBB);
197 void ExitScope(MachineBasicBlock *MBB);
559 MachineBasicBlock *MBB = MI->getParent();
560 Preheader->splice(Preheader->getFirstTerminator(), MBB, MI);
571 /// Check if this mbb is guaranteed to execute. If not then a load from this mbb
592 void MachineLICM::EnterScope(MachineBasicBlock *MBB) {
[all...] |
| MachineVerifier.cpp | 99 // Is this MBB reachable from the MF entry point?
106 // Regs killed in MBB. They may be defined again, and will then be in both
110 // Regs defined in MBB and live out. Note that vregs passing through may
114 // Vregs that pass through MBB untouched. This set is disjoint from
118 // Vregs that must pass through MBB because they are needed by a successor
180 // Extra register info per MBB.
198 void visitMachineBasicBlockBefore(const MachineBasicBlock *MBB);
204 void visitMachineBasicBlockAfter(const MachineBasicBlock *MBB);
211 void report(const char *msg, const MachineBasicBlock *MBB);
224 void markReachable(const MachineBasicBlock *MBB);
[all...] |
| PeepholeOptimizer.cpp | 151 bool optimizeCmpInstr(MachineInstr *MI, MachineBasicBlock *MBB);
152 bool optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
165 bool foldImmediate(MachineInstr *MI, MachineBasicBlock *MBB,
413 optimizeExtInstr(MachineInstr *MI, MachineBasicBlock *MBB,
490 if (UseMBB == MBB) {
498 } else if (Aggressive && DT->dominates(MBB, UseMBB)) {
503 // Both will be live out of the def MBB anyway. Don't extend live range of
563 MachineBasicBlock *MBB) {
722 MachineBasicBlock *MBB = OrigPHI->getParent();
723 MachineInstrBuilder MIB = BuildMI(*MBB, OrigPHI, OrigPHI->getDebugLoc()
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ControlFlowFinalizer.cpp | 316 MakeFetchClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
323 for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
336 MachineInstr *MIb = BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead),
372 MachineBasicBlock *MBB = InsertPos->getParent();
376 InsertPos = BuildMI(MBB, InsertPos->getDebugLoc(),
385 MakeALUClause(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I)
390 for (MachineBasicBlock::instr_iterator E = MBB.instr_end(); I != E;) {
421 MachineInstr *MILit = BuildMI(MBB, I, I->getDebugLoc(),
484 MachineBasicBlock &MBB = *MB
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonStoreWidening.cpp | 90 void createStoreGroups(MachineBasicBlock &MBB,
92 bool processBasicBlock(MachineBasicBlock &MBB);
209 void HexagonStoreWidening::createStoreGroups(MachineBasicBlock &MBB,
216 for (auto &I : MBB)
490 MachineBasicBlock *MBB = OG.back()->getParent();
491 MachineBasicBlock::iterator InsertAt = MBB->end();
505 for (auto &I : *MBB) {
512 assert((InsertAt != MBB->end()) && "Cannot locate any store from the group");
520 if (InsertAt != MBB->begin())
531 InsertAt = MBB->begin()
[all...] |
