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/external/chromium-trace/catapult/third_party/py_vulcanize/third_party/rcssmin/tests/yui/
bug2527974.css.min	`1 /! $LastChangedRevision: 81 $ $LastChangedDate: 2009-05-27 17:41:02 +0100 (Wed, 27 May 2009) $ /body{yo:cats}ul[id$=foo] label:hover{yo:yo`
bug2527974.css	`5 /! $LastChangedRevision: 81 $ $LastChangedDate: 2009-05-27 17:41:02 +0100 (Wed, 27 May 2009) $ /`
/external/chromium-trace/catapult/third_party/py_vulcanize/third_party/rcssmin/tests/yui/out/
bug2527974.out.b	`1 /! $LastChangedRevision: 81 $ $LastChangedDate: 2009-05-27 17:41:02 +0100 (Wed, 27 May 2009) $ /body{yo:cats}ul[id$=foo] label:hover{yo:yo`
/prebuilts/gdb/darwin-x86/lib/python2.7/email/test/data/
msg_46.txt	`2 Delivery-Date: Mon, 08 Feb 2010 14:05:16 +0100 5 id UNIQUE for someone@example.com; Mon, 08 Feb 2010 14:05:16 +0100 6 Date: Mon, 01 Feb 2010 12:21:16 +0100 15 Date: Mon, 01 Feb 2010 12:18:40 +0100`
/prebuilts/gdb/linux-x86/lib/python2.7/email/test/data/
msg_46.txt	`2 Delivery-Date: Mon, 08 Feb 2010 14:05:16 +0100 5 id UNIQUE for someone@example.com; Mon, 08 Feb 2010 14:05:16 +0100 6 Date: Mon, 01 Feb 2010 12:21:16 +0100 15 Date: Mon, 01 Feb 2010 12:18:40 +0100`
/prebuilts/python/darwin-x86/2.7.5/lib/python2.7/email/test/data/
msg_46.txt	`2 Delivery-Date: Mon, 08 Feb 2010 14:05:16 +0100 5 id UNIQUE for someone@example.com; Mon, 08 Feb 2010 14:05:16 +0100 6 Date: Mon, 01 Feb 2010 12:21:16 +0100 15 Date: Mon, 01 Feb 2010 12:18:40 +0100`
/prebuilts/python/linux-x86/2.7.5/lib/python2.7/email/test/data/
msg_46.txt	`2 Delivery-Date: Mon, 08 Feb 2010 14:05:16 +0100 5 id UNIQUE for someone@example.com; Mon, 08 Feb 2010 14:05:16 +0100 6 Date: Mon, 01 Feb 2010 12:21:16 +0100 15 Date: Mon, 01 Feb 2010 12:18:40 +0100`
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-scripts/
assign-loc.d	`6 0+0100 A HEAP_SIZE`
/external/libusb-compat/
ChangeLog	`3 Date: Thu Jul 9 22:15:32 2009 +0100 9 Date: Thu Jul 9 22:13:45 2009 +0100 20 Date: Fri Jun 19 22:11:02 2009 +0100 43 Date: Thu Jun 11 23:50:59 2009 +0100 130 Date: Mon May 26 00:05:32 2008 +0100 136 Date: Fri May 23 16:01:18 2008 +0100 142 Date: Fri May 23 15:32:30 2008 +0100 153 Date: Tue May 20 16:27:17 2008 +0100 161 Date: Mon May 19 16:15:17 2008 +0100 173 Date: Mon May 19 15:21:04 2008 +0100 [all...]`
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/sh/arch/
sh4a-nofpu.s	18 movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 /{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} 19 movua.l @r5+,r0 ;!/ 0100mmmm11101001 movua.l @<REG_M>+,r0 /{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} 48 cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 49 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 58 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 59 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 60 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 61 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 62 ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} 63 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up [all...]
sh3e.s	41 cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 42 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 51 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 52 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 53 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 54 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 55 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} 56 ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 57 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} 58 ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nom (…) [all...]
sh4-nofpu.s	41 cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 42 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 51 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 52 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 53 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 54 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 55 ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} 56 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} 57 ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 58 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu (…) [all...]
sh4-nommu-nofpu.s	15 ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} 16 ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} 17 ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} 18 ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} 25 stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} 26 stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} 53 cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 54 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 63 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 64 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up [all...]
sh-dsp.s	15 ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD /{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} 16 ldc r4,RE ;!/ 0100nnnn01111110 ldc <REG_N>,RE /{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} 17 ldc r4,RS ;!/ 0100nnnn01101110 ldc <REG_N>,RS /{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} 18 ldc.l @r4+,MOD ;!/ 0100nnnn01010111 ldc.l @<REG_N>+,MOD /{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} 19 ldc.l @r4+,RE ;!/ 0100nnnn01110111 ldc.l @<REG_N>+,RE /{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} 20 ldc.l @r4+,RS ;!/ 0100nnnn01100111 ldc.l @<REG_N>+,RS /{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} 23 lds r4,DSR ;!/ 0100nnnn01101010 lds <REG_N>,DSR /{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} 24 lds r4,A0 ;!/ 0100nnnn01111010 lds <REG_N>,A0 /{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} 25 lds r4,X0 ;!/ 0100nnnn10001010 lds <REG_N>,X0 /{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} 26 lds r4,X1 ;!/ 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up [all...]
sh3-nommu.s	15 ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 16 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} 17 ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} 18 ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} 19 ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} 20 ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} 24 stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} 25 stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} 26 stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} 53 cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up [all...]
sh3.s	42 cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 43 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 52 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 53 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 54 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 55 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 56 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} 57 ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 58 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} 59 ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nom (…) [all...]
sh2a-nofpu.s	15 ldc r5,TBR ;!/* 0100mmmm01001010 ldc <REG_M>,TBR /{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up} 16 mov.b R0,@r4+ ;!/ 0100nnnn10001011 mov.b R0,@<REG_N>+ /{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up} 17 mov.b @-r5,R0 ;!/ 0100nnnn11001011 mov.b @-<REG_M>,R0 /{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up} 19 mov.b @(2048,r5),r4 ;!/ 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> / {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up \| arch_op32} 20 mov.l R0,@r4+ ;!/ 0100nnnn10101011 mov.l R0,@<REG_N>+ /{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up} 21 mov.l @-r5,R0 ;!/ 0100nnnn11001011 mov.l @-<REG_M>,R0 /{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up} 24 mov.w R0,@r4+ ;!/ 0100nnnn10011011 mov.w R0,@<REG_N>+ /{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up} 25 mov.w @-r5,R0 ;!/ 0100nnnn11011011 mov.w @-<REG_M>,R0 /{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up} 37 clips.b r4 ;!/ 0100nnnn10010001 clips.b <REG_N> / {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up} 38 clips.w r4 ;!/ 0100nnnn10010101 clips.w <REG_N> */ {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nof (…) [all...]
sh4a.s	42 cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 43 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 53 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 54 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 55 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 56 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 57 ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} 58 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} 59 ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 60 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu (…) [all...]
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-sh/arch/
sh4a-nofpu.s	18 movua.l @r5,r0 ;!/* 0100mmmm10101001 movua.l @<REG_M>,r0 /{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofpu_up} 19 movua.l @r5+,r0 ;!/ 0100mmmm11101001 movua.l @<REG_M>+,r0 /{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofpu_up} 48 cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 49 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 58 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 59 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 60 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 61 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 62 ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} 63 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up [all...]
sh3e.s	41 cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 42 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 51 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 52 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 53 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 54 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 55 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} 56 ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 57 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} 58 ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nom (…) [all...]
sh4-nofpu.s	41 cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 42 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 51 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 52 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 53 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 54 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 55 ldc r4,SGR ;!/ 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} 56 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} 57 ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 58 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu (…) [all...]
sh4-nommu-nofpu.s	15 ldc r4,SGR ;!/* 0100nnnn00111010 ldc <REG_N>,SGR /{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up} 16 ldc r4,DBR ;!/ 0100nnnn11111010 ldc <REG_N>,DBR /{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up} 17 ldc.l @r4+,SGR ;!/ 0100nnnn00110110 ldc.l @<REG_N>+,SGR /{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up} 18 ldc.l @r4+,DBR ;!/ 0100nnnn11110110 ldc.l @<REG_N>+,DBR /{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up} 25 stc.l SGR,@-r4 ;!/ 0100nnnn00110010 stc.l SGR,@-<REG_N> /{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up} 26 stc.l DBR,@-r4 ;!/ 0100nnnn11110010 stc.l DBR,@-<REG_N> /{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up} 53 cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 54 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 63 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 64 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up [all...]
sh-dsp.s	15 ldc r4,MOD ;!/* 0100nnnn01011110 ldc <REG_N>,MOD /{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up} 16 ldc r4,RE ;!/ 0100nnnn01111110 ldc <REG_N>,RE /{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up} 17 ldc r4,RS ;!/ 0100nnnn01101110 ldc <REG_N>,RS /{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up} 18 ldc.l @r4+,MOD ;!/ 0100nnnn01010111 ldc.l @<REG_N>+,MOD /{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up} 19 ldc.l @r4+,RE ;!/ 0100nnnn01110111 ldc.l @<REG_N>+,RE /{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up} 20 ldc.l @r4+,RS ;!/ 0100nnnn01100111 ldc.l @<REG_N>+,RS /{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up} 23 lds r4,DSR ;!/ 0100nnnn01101010 lds <REG_N>,DSR /{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up} 24 lds r4,A0 ;!/ 0100nnnn01111010 lds <REG_N>,A0 /{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up} 25 lds r4,X0 ;!/ 0100nnnn10001010 lds <REG_N>,X0 /{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up} 26 lds r4,X1 ;!/ 0100nnnn10011010 lds <REG_N>,X1 */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up [all...]
sh3-nommu.s	15 ldc r4,SSR ;!/* 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 16 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} 17 ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK /{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up} 18 ldc.l @r4+,SSR ;!/ 0100nnnn00110111 ldc.l @<REG_N>+,SSR /{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up} 19 ldc.l @r4+,SPC ;!/ 0100nnnn01000111 ldc.l @<REG_N>+,SPC /{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up} 20 ldc.l @r4+,r1_bank ;!/ 0100nnnn1xxx0111 ldc.l @<REG_N>+,Rn_BANK /{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up} 24 stc.l SSR,@-r4 ;!/ 0100nnnn00110011 stc.l SSR,@-<REG_N> /{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up} 25 stc.l SPC,@-r4 ;!/ 0100nnnn01000011 stc.l SPC,@-<REG_N> /{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up} 26 stc.l r1_bank,@-r4 ;!/ 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> /{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up} 53 cmp/pl r4 ;!/ 0100nnnn00010101 cmp/pl <REG_N> */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up [all...]
sh3.s	42 cmp/pl r4 ;!/* 0100nnnn00010101 cmp/pl <REG_N> /{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh_up} 43 cmp/pz r4 ;!/ 0100nnnn00010001 cmp/pz <REG_N> /{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh_up} 52 jmp @r4 ;!/ 0100nnnn00101011 jmp @<REG_N> /{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh_up} 53 jsr @r4 ;!/ 0100nnnn00001011 jsr @<REG_N> /{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh_up} 54 ldc r4,SR ;!/ 0100nnnn00001110 ldc <REG_N>,SR /{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh_up} 55 ldc r4,GBR ;!/ 0100nnnn00011110 ldc <REG_N>,GBR /{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh_up} 56 ldc r4,VBR ;!/ 0100nnnn00101110 ldc <REG_N>,VBR /{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh_up} 57 ldc r4,SSR ;!/ 0100nnnn00111110 ldc <REG_N>,SSR /{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up} 58 ldc r4,SPC ;!/ 0100nnnn01001110 ldc <REG_N>,SPC /{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up} 59 ldc r4,r1_bank ;!/ 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nom (…) [all...]

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