| /external/llvm/test/ExecutionEngine/OrcMCJIT/ |
| non-extern-addend.ll | 6 %d.top64 = lshr i64 %d.int64, 32
|
| /external/llvm/test/ExecutionEngine/ |
| test-interp-vec-shift.ll | 17 %tr1 = lshr <2 x i32> <i32 1, i32 2>, %shift.upgrd.6
18 %tr2 = lshr <2 x i32> <i32 1, i32 2>, <i32 5, i32 6>
25 %tr1.u = lshr <2 x i64> <i64 1, i64 2>, <i64 5, i64 6>
27 %tr2.u = lshr <2 x i64> <i64 1, i64 2>, %shift.upgrd.9
|
| /external/llvm/test/Transforms/ConstProp/ |
| 2009-06-20-constexpr-zero-lhs.ll | 8 @test5 = constant i32 lshr (i32 0, i32 ptrtoint (i32* @G to i32))
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2006-09-15-CastToBool.ll | 7 %tmp2.ui = lshr i32 %tmp, 5 ; <i32> [#uses=1]
|
| 2008-07-13-DivZero.ll | 1 ; RUN: opt < %s -instcombine -S | grep "lshr.*3"
|
| pr19420.ll | 34 %a = lshr i32 %x, 4
41 %a = lshr <2 x i32> %x, <i32 5, i32 5>
51 %a = lshr i32 %x, 4
59 %a = lshr <2 x i32> %x, <i32 4, i32 4>
|
| udiv_select_to_select_shift.ll | 6 ; RUN: grep lshr %t | count 2
|
| apint-shift.ll | 38 %B = lshr i55 %A, 55 ; <i55> [#uses=1]
85 %C = lshr i17 %B, 16 ; <i17> [#uses=1]
92 %B = lshr i19 %A, 18 ; <i19> [#uses=1]
102 %B = lshr i23 %a, 11 ; <i23> [#uses=1]
128 %B = lshr i35 %A, 4 ; <i35> [#uses=1]
139 %D = lshr i79 %C, 4 ; <i79> [#uses=1]
172 %B = lshr i106 %A, 3 ; <i106> [#uses=1]
180 %B = lshr i11 %A, 10 ; <i11> [#uses=1]
237 %x = lshr i37 %AA, 17 ; <i37> [#uses=1]
238 %tmp.3 = lshr i37 %tmp.2, 17 ; <i37> [#uses=1
[all...] |
| /external/llvm/test/Transforms/InstSimplify/ |
| shr-nop.ll | 17 %shr = lshr exact i8 0, %a
41 %shr = lshr exact i8 0, %a
57 %shr = lshr i8 0, %a
73 %shr = lshr exact i8 128, %a
89 %shr = lshr i8 0, %a
97 %shr = lshr exact i8 128, %a
113 %shr = lshr i8 128, %a
129 %shr = lshr i8 128, %a
145 %shr = lshr i8 0, %a
161 %shr = lshr i8 0, %
[all...] |
| /external/llvm/test/Transforms/LoopUnroll/ |
| 2011-08-09-IVSimplify.ll | 14 ; CHECK: %shr.1 = lshr i32 %bit_addr.addr.01, 5
16 ; CHECK: %shr.2 = lshr i32 %bit_addr.addr.01, 5
18 ; CHECK: %shr.3 = lshr i32 %bit_addr.addr.01, 5
28 %shr = lshr i32 %bit_addr.addr.01, 5
|
| /external/llvm/test/Transforms/SimplifyCFG/ |
| branch-fold.ll | 33 %shr.i4.i = lshr i64 %i0, 48
35 %shr.i.i = lshr i64 %i1, 48
42 %shr.i13.i9 = lshr i64 %i1, 48
44 %shr.i.i11 = lshr i64 %i0, 48
|
| /external/llvm/test/CodeGen/X86/ |
| x86-shifts.ll | 24 %B = lshr <4 x i32> %A, < i32 2, i32 2, i32 2, i32 2>
25 %C = lshr <4 x i32> %A, < i32 1, i32 1, i32 1, i32 1>
60 %B = lshr <2 x i64> %A, < i64 8, i64 8>
61 %C = lshr <2 x i64> %A, < i64 1, i64 1>
85 %B = lshr <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2>
86 %C = lshr <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
131 %B = lshr <2 x i64> %A, < i64 8, i64 1>
132 %C = lshr <2 x i64> %A, < i64 1, i64 0>
156 %B = lshr <2 x i32> %A, < i32 8, i32 8>
157 %C = lshr <2 x i32> %A, < i32 1, i32 1
[all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-shifts.c | 9 // CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
27 // CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
|
| arm-neon-shifts.c | 11 // CHECK: %{{.*}} = lshr <8 x i8> %a, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
29 // CHECK: %[[SHR:.*]] = lshr <8 x i8> %b, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
|
| /external/clang/test/CodeGenObjC/ |
| bitfield-access.m | 19 // CHECK-I386: lshr i8 [[t0_0]], 7
31 // CHECK-ARM: [[t1_1:%.*]] = lshr i40 [[t1_0]], 1
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| vshift-lshr-cost.ll | 22 %shift = lshr <2 x i64> %a, %b
34 %shift = lshr <4 x i64> %a, %b
46 %shift = lshr <4 x i32> %a, %b
58 %shift = lshr <8 x i32> %a, %b
69 %shift = lshr <8 x i16> %a, %b
80 %shift = lshr <16 x i16> %a, %b
91 %shift = lshr <16 x i8> %a, %b
102 %shift = lshr <32 x i8> %a, %b
119 %shift = lshr <2 x i64> %a, %splat
132 %shift = lshr <4 x i64> %a, %spla
[all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| rotl.i64.ll | 14 %2 = lshr i64 %x, %1
35 %tmp2 = lshr i64 %x, %tmp1
|
| /external/llvm/test/CodeGen/MIR/PowerPC/ |
| unordered-implicit-registers.mir | 12 %shr.i.1 = lshr i32 2072, %lnot.ext.1
13 %call.lobit.1 = lshr i32 %shr.i.1, 7
|
| /external/llvm/test/CodeGen/MSP430/ |
| shifts.ll | 9 %shr = lshr i8 %a, %cnt
33 %shr = lshr i16 %a, %cnt
|
| /external/llvm/test/CodeGen/Mips/ |
| micromips-shift.ll | 33 %shr = lshr i32 %0, 4
37 %shr1 = lshr i32 %1, 10
|
| /external/llvm/test/CodeGen/PowerPC/ |
| rlwimi3.ll | 18 %tmp21 = lshr i32 %tmp19, 5 ; <i32> [#uses=1]
21 %tmp23 = lshr i32 %tmp19, 20 ; <i32> [#uses=1]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-add5.ll | 21 %tmp = lshr i32 %b, 6
38 %r8 = lshr i32 %a, 8
|
| thumb2-and.ll | 21 %tmp = lshr i32 %b, 6
38 %r8 = lshr i32 %a, 8
|
| thumb2-cmp2.ll | 31 %tmp = lshr i32 %b, 6
48 %r8 = lshr i32 %a, 8
|
| thumb2-mvn2.ll | 28 %tmp = lshr i32 %a, 6
45 %r8 = lshr i32 %a, 8
|
