| /external/llvm/test/CodeGen/AMDGPU/ |
| rotl.ll | 17 %2 = lshr i32 %x, %1
33 %2 = lshr <2 x i32> %x, %1
53 %2 = lshr <4 x i32> %x, %1
|
| literals.ll | 10 ; CHECK: LSHR
27 ; CHECK: LSHR
|
| /external/llvm/test/CodeGen/X86/ |
| 2009-10-19-EmergencySpill.ll | 17 %6 = lshr i64 %5, 48 ; <i64> [#uses=1]
20 %8 = lshr i64 %5, 8 ; <i64> [#uses=1]
40 %13 = lshr i32 %12, 24 ; <i32> [#uses=1]
|
| lsr-loop-exit-cond.ll | 33 %3 = lshr i32 %s0.0, 24 ; <i32> [#uses=1]
37 %7 = lshr i32 %s1.0, 16 ; <i32> [#uses=1]
48 %17 = lshr i32 %s1.0, 24 ; <i32> [#uses=1]
62 %30 = lshr i32 %16, 24 ; <i32> [#uses=1]
73 %36 = lshr i32 %29, 16 ; <i32> [#uses=1]
81 %44 = lshr i32 %29, 24 ; <i32> [#uses=1]
104 %59 = lshr i32 %29, 16 ; <i32> [#uses=1]
113 %68 = lshr i32 %29, 8 ; <i32> [#uses=1]
129 %83 = lshr i32 %67, 24 ; <i32> [#uses=1]
132 %85 = lshr i32 %67, 16 ; <i32> [#uses=1
[all...] |
| x86-64-double-shifts-Oz-Os-O2.ll | 17 %shr = lshr i64 %b, 54
39 %shr = lshr i64 %b, 53
61 %shr = lshr i64 %b, 52
|
| 2008-12-19-EarlyClobberBug.ll | 17 %2 = lshr i64 %u, 32 ; <i64> [#uses=1]
24 %6 = lshr i64 %v, 32 ; <i64> [#uses=1]
|
| 2012-10-18-crash-dagco.ll | 43 %tmp45 = lshr i32 %tmp44, 8
44 %tmp46 = lshr i32 %tmp44, 7
|
| i128-mul.ll | 9 %tmp3 = lshr i128 %tmp2, %tmp7
38 %shr = lshr i128 %add, 64
|
| /external/llvm/test/Transforms/InstCombine/ |
| div.ll | 17 ; CHECK-NEXT: lshr i32 %A, 3
87 ; CHECK-NEXT: lshr i32 %X
96 ; CHECK-NEXT: lshr i32 %X
125 %div = lshr i32 %shl, 2
130 ; CHECK-NEXT: lshr i32 %a,
135 %shr = lshr <2 x i64> %x, <i64 5, i64 5>
211 ; CHECK-NEXT: %div = lshr i32 %a, 2
269 %shr = lshr <2 x i32> %x, <i32 31, i32 31>
278 %div = lshr i32 %shl, 2
283 ; CHECK-NEXT: %[[shr:.*]] = lshr i32 %[[shl]],
[all...] |
| sext.ll | 54 %u = lshr i32 %x, 3
72 %d = lshr i32 %f, 24
78 ; CHECK: %d = lshr i32 %f, 24
131 %shr = lshr i32 %x, 1
146 ; CHECK-NEXT: %and = lshr i32 %x, 3
158 ; CHECK-NEXT: %and = lshr i16 %x, 4
|
| /external/clang/test/CodeGen/ |
| x86_32-xsave.c | 20 // XSAVE: [[high64_1:%[0-9a-zA-z]+]] = lshr i64 [[tmp_ULLi_1]], 32
28 // XSAVE: [[high64_3:%[0-9a-zA-z]+]] = lshr i64 [[tmp_ULLi_3]], 32
38 // XSAVEOPT: [[high64_1:%[0-9a-zA-z]+]] = lshr i64 [[tmp_ULLi_1]], 32
48 // XSAVEC: [[high64_1:%[0-9a-zA-z]+]] = lshr i64 [[tmp_ULLi_1]], 32
58 // XSAVES: [[high64_1:%[0-9a-zA-z]+]] = lshr i64 [[tmp_ULLi_1]], 32
66 // XSAVES: [[high64_3:%[0-9a-zA-z]+]] = lshr i64 [[tmp_ULLi_3]], 32
|
| arm-crc32.c | 49 // CHECK: [[T1:%[0-9]+]] = lshr i64 %b, 32
59 // CHECK: [[T1:%[0-9]+]] = lshr i64 %b, 32
|
| /external/llvm/test/CodeGen/Hexagon/ |
| bit-loop.ll | 20 %v.sroa.4.0.extract.shift = lshr i64 %0, 16
22 %v.sroa.5.0.extract.shift = lshr i64 %0, 32
24 %v.sroa.6.0.extract.shift = lshr i64 %0, 48
55 %v.sroa.4.0.extract.shift35 = lshr i64 %2, 16
57 %v.sroa.5.0.extract.shift37 = lshr i64 %2, 32
59 %v.sroa.6.0.extract.shift39 = lshr i64 %2, 48
|
| brev_ld.ll | 25 %shr1 = lshr i32 %conv, 1
45 %shr1 = lshr i32 %conv, 1
65 %shr1 = lshr i32 %conv, 1
85 %shr1 = lshr i32 %conv, 1
105 %shr1 = lshr i32 %conv, 1
123 %shr1 = lshr i32 %conv, 1
|
| /external/llvm/test/CodeGen/AArch64/ |
| xbfiz.ll | 23 %shr = lshr i64 %shl, 17
31 %shr = lshr i32 %shl, 2
|
| /external/llvm/test/CodeGen/ARM/ |
| mulhi.ll | 17 %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
34 %tmp3 = lshr i64 %tmp2, 32 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/Generic/ |
| i128-addsub.ll | 16 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
35 %tmp21 = lshr i128 %tmp15, 64 ; <i128> [#uses=1]
|
| /external/llvm/test/CodeGen/PowerPC/ |
| rlwimi2.ll | 21 %tmp.27 = lshr i32 %tmp.23, 5 ; <i32> [#uses=1]
24 %tmp.33 = lshr i32 %tmp.23, 20 ; <i32> [#uses=1]
|
| rlwinm.ll | 30 %tmp.3 = lshr i32 %a, 8 ; <i32> [#uses=1]
52 %tmp.2 = lshr i32 %tmp.1, 8 ; <i32> [#uses=1]
|
| /external/llvm/test/CodeGen/SystemZ/ |
| shift-09.ll | 31 %shift = lshr i32 %b, %add
41 %shift = lshr i32 %a, %add
|
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-eor.ll | 35 %tmp = lshr i32 %b, 6
52 %r8 = lshr i32 %a, 8
|
| thumb2-orn.ll | 45 %tmp = lshr i32 %b, 6
64 %r8 = lshr i32 %a, 8
|
| thumb2-sbc.ll | 61 %ch = lshr i64 %carry, 32
65 %ph = lshr i64 %prod, 32
|
| thumb2-teq2.ll | 34 %tmp = lshr i32 %b, 6
53 %r8 = lshr i32 %a, 8
|
| thumb2-tst2.ll | 34 %tmp = lshr i32 %b, 6
53 %r8 = lshr i32 %a, 8
|
