| /external/llvm/test/CodeGen/X86/ |
| 2006-10-10-FindModifiedNodeSlotBug.ll | 15 %tmp15 = lshr i32 %tmp14, 31 ; <i32> [#uses=1]
|
| 2008-10-13-CoalescerBug.ll | 18 %5 = lshr i32 %2, %2 ; <i32> [#uses=3]
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| 2009-04-scale.ll | 12 %1 = lshr i32 %0, 8 ; <i32> [#uses=1]
|
| 2010-09-01-RemoveCopyByCommutingDef.ll | 19 %btmp3 = lshr i64 %x1, 32 ; <i64> [#uses=1]
|
| 2012-07-15-vshl.ll | 14 %bitop = lshr <16 x i32> zeroinitializer, %smear.15
|
| call-push.ll | 16 %tmp514 = lshr i32 %tmp4, 24 ; <i32> [#uses=1]
|
| constant-combines.ll | 25 %5 = lshr i64 %3, 32
|
| lea.ll | 24 %tmp6 = lshr i32 %tmp, 2
|
| legalize-shl-vec.ll | 22 %Out = lshr <2 x i256> %In, %Amt
|
| movmsk.ll | 22 %tmp1 = lshr i64 %tmp, 63
41 %tmp1 = lshr i64 %tmp, 63
59 %shr.i = lshr i32 %2, 31
77 %shr.i = lshr i32 %2, 31
|
| tbm_patterns.ll | 8 %0 = lshr i32 %a, 4
19 %1 = lshr i32 %0, 4
29 %0 = lshr i64 %a, 4
40 %1 = lshr i64 %0, 4
|
| 2007-10-19-SpillerUnfold.ll | 39 %tmp253444 = lshr i32 %tmp180181, 4 ; <i32> [#uses=1]
76 %tmp405 = lshr i32 %tmp396, 31 ; <i32> [#uses=1]
78 %tmp409 = lshr i32 %tmp406, %tmp398 ; <i32> [#uses=1]
|
| vector-rotate-128.ll | 105 %lshr = lshr <2 x i64> %a, %b64
106 %or = or <2 x i64> %shl, %lshr
251 %lshr = lshr <4 x i32> %a, %b32
252 %or = or <4 x i32> %shl, %lshr
512 %lshr = lshr <8 x i16> %a, %b16
513 %or = or <8 x i16> %shl, %lshr
721 %lshr = lshr <16 x i8> %a, %b
[all...] |
| vector-rotate-256.ll | 68 %lshr = lshr <4 x i64> %a, %b64
69 %or = or <4 x i64> %shl, %lshr
146 %lshr = lshr <8 x i32> %a, %b32
147 %or = or <8 x i32> %shl, %lshr
263 %lshr = lshr <16 x i16> %a, %b16
264 %or = or <16 x i16> %shl, %lshr
381 %lshr = lshr <32 x i8> %a, %b
[all...] |
| /external/llvm/test/Transforms/IndVarSimplify/ |
| loop_evaluate11.ll | 27 %tmp6 = lshr i32 undef, %tmp5 ; <i32> [#uses=1]
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2007-03-25-BadShiftMask.ll | 17 %tmp8 = lshr i32 %tmp7, 21 ; <i32> [#uses=1]
|
| apint-and-or-and.ll | 33 %B = lshr i67 %Y, 66
|
| xor2.ll | 61 %shr = lshr i32 %xor, 8
66 ; CHECK: lshr i32 %val1, 8
78 %shr = lshr i32 %xor, 16
82 ; CHECK: lshr i32 %x, 16
|
| /external/llvm/test/CodeGen/ARM/ |
| vshrn.ll | 7 %tmp2 = lshr <8 x i16> %tmp1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
45 %tmp2 = lshr <4 x i32> %tmp1, <i32 17, i32 17, i32 17, i32 17>
55 %tmp2 = lshr <2 x i64> %tmp1, <i64 33, i64 33>
|
| /external/llvm/test/Transforms/CodeGenPrepare/X86/ |
| x86-shuffle-sink.ll | 89 ; CHECK-AVX2: lshr <2 x i64> %lhs, %mask
94 ; CHECK-SSE2: lshr <2 x i64> %lhs, [[SPLAT]]
103 %res = lshr <2 x i64> %lhs, %mask
|
| /external/llvm/test/Transforms/GVN/ |
| load-pre-nonlocal.ll | 58 ; CHECK: [[LSHR:%[0-9]+]] = lshr i64 %0, 32, !dbg [[LSHR_LOC:![0-9]+]]
59 ; CHECK: trunc i64 [[LSHR]] to i32
|
| /external/llvm/test/Transforms/LoopVectorize/ |
| if-conversion-edgemasks.ll | 37 %and.i.i = lshr i32 %3, 2
54 %p1.addr.0.lobit.i = lshr i32 %p1.addr.0.i, 31
73 %and17.i = lshr i32 %p1.addr.2.i, 3
97 %p1.addr.0.lobit.i.i = lshr i32 %p1.addr.0.i21.i, 31
118 %and17.i.i = lshr i32 %p1.addr.2.i.i, 3
129 %and.i12.i = lshr i32 %p1.addr.3.i.i, 2
142 %and.i.i18 = lshr i32 %10, 2
162 %p1.addr.0.lobit.i68 = lshr i32 %p1.addr.0.i64, 31
181 %and17.i81 = lshr i32 %p1.addr.2.i77, 3
199 %p1.addr.0.lobit.i.i34 = lshr i32 %p1.addr.0.i21.i30, 3
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonGenExtract.cpp | 92 // (and (shl (lshr x, #sr), #sl), #m)
115 // (and (lshr x, #sr), #m)
130 // (shl (lshr x, #sr), #sl)
161 APInt A = APInt(BW, ~0ULL).lshr(SR).shl(SL);
167 APInt M = CM->getValue().lshr(SL);
|
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-simd-shift.ll | 55 %vshr_n = lshr <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
62 %vshr_n = lshr <4 x i16> %a, <i16 3, i16 3, i16 3, i16 3>
69 %vshr_n = lshr <2 x i32> %a, <i32 3, i32 3>
76 %vshr_n = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
83 %vshr_n = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
90 %vshr_n = lshr <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
97 %vshr_n = lshr <2 x i64> %a, <i64 3, i64 3>
160 %vsra_n = lshr <8 x i8> %b, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
168 %vsra_n = lshr <4 x i16> %b, <i16 3, i16 3, i16 3, i16 3>
176 %vsra_n = lshr <2 x i32> %b, <i32 3, i32 3
[all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| sra.ll | 75 ;EG-DAG: LSHR {{\*? *}}[[LOSMTMP:T[0-9]+\.[XYZW]]], [[OPLO:T[0-9]+\.[XYZW]]], [[SHIFT]]
109 ;EG-DAG: LSHR {{.*}}, [[SHA]]
110 ;EG-DAG: LSHR {{.*}}, [[SHB]]
160 ;EG-DAG: LSHR {{.*}}, [[SHA]]
161 ;EG-DAG: LSHR {{.*}}, [[SHB]]
162 ;EG-DAG: LSHR {{.*}}, [[SHA]]
163 ;EG-DAG: LSHR {{.*}}, [[SHB]]
|
