| /toolchain/binutils/binutils-2.25/cpu/ |
| cris.cpu | [all...] |
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 148 /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
168 const uint16_t *SubRegIndices; // Pointer to the subreg lookup
170 const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
172 unsigned NumSubRegIndices; // Number of subreg indices.
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| /external/llvm/lib/CodeGen/ |
| RegisterCoalescer.h | 87 /// the full register, but was a subreg operation.
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| DeadMachineInstructionElim.cpp | 143 // Check the subreg set, not the alias set, because a def
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| ScheduleDAGInstrs.cpp | 373 unsigned SubReg = MO.getSubReg();
374 if (SubReg == 0)
376 return TRI->getSubRegIndexLaneMask(SubReg);
[all...] |
| TargetInstrInfo.cpp | [all...] |
| TwoAddressInstructionPass.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 89 /// EmitSubregNode - Generate machine code for subreg nodes.
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| InstrEmitter.cpp | 466 /// EmitSubregNode - Generate machine code for subreg nodes.
625 unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
626 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
725 // Handle subreg insert/extract specially
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 102 // Don't change the register if there's an implicit def of a subreg or
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| AArch64ISelDAGToDAG.cpp | 552 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
554 dl, MVT::i32, N, SubReg);
761 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
765 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.h | 101 /// SubReg index.
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| SIFixSGPRCopies.cpp | 200 unsigned SubReg = CopyUse.getOperand(1).getSubReg();
201 if (SubReg != AMDGPU::NoSubRegister)
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| SIInstrInfo.cpp | 953 unsigned SubReg = Src0.getSubReg();
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.h | 183 unsigned SubReg,
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| /external/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 252 // Expand any composed subreg indices.
254 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
255 // expanded subreg indices recursively.
270 // Add I->second as a name for the subreg SRI->second, assuming it is
283 // Consider this subreg sequence:
294 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
306 // Compute the inverse SubReg -> Idx map.
418 const CodeGenRegister *SubReg = I->second;
419 const CodeGenRegister::SuperRegList &Leads = SubReg->LeadingSuperRegs
[all...] |
| CodeGenRegisters.h | 77 // Map of composite subreg indices.
81 // Returns the subreg index that results from composing this with Idx.
88 // Add a composite subreg index: this+A = B.
95 // Synthetic subreg indices that aren't contiguous (for instance ARM
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| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 66 unsigned SubReg = 0) const {
76 SubReg,
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| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 76 // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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| /external/llvm/lib/Target/PowerPC/ |
| PPCSubtarget.cpp | 36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
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| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/ |
| timevar.def | 195 DEFTIMEVAR (TV_LOWER_SUBREG , "lower subreg")
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| output.h | 75 /* Replace a SUBREG with a REG or a MEM, based on the thing it is a
76 subreg of. */
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| /external/llvm/lib/CodeGen/MIRParser/ |
| MIParser.cpp | 120 bool parseSubRegisterIndex(unsigned &SubReg);
853 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
859 SubReg = getSubRegIndex(Name);
860 if (!SubReg)
930 unsigned SubReg = 0;
932 if (parseSubRegisterIndex(SubReg))
944 Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrVector.td | 43 // subreg of the result.
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86AsmPrinter.cpp | 219 if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) {
|
