| /external/llvm/test/CodeGen/AArch64/ |
| breg.ll | 1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu -aarch64-atomic-cfg-tidy=0 | FileCheck %s
|
| init-array.ll | 1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
2 ; RUN: llc -mtriple=aarch64-none-none-eabi -verify-machineinstrs -o - %s | FileCheck %s
|
| large_shift.ll | 1 ; RUN: llc -march=aarch64 -o - %s
4 ; Make sure we don't run into an assert in the aarch64 code selection when
|
| mature-mc-support.ll | 4 ; RUN: not llc -mtriple=aarch64-pc-linux < %s > /dev/null 2> %t3
7 ; RUN: not llc -mtriple=aarch64-pc-linux -filetype=obj < %s > /dev/null 2> %t4
|
| arm64-vqadd.ll | 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
35 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
44 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
53 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
80 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2
[all...] |
| arm64-crypto.ll | 1 ; RUN: llc -march=arm64 -mattr=crypto -aarch64-neon-syntax=apple -o - %s | FileCheck %s
3 declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
4 declare <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
5 declare <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
6 declare <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
11 %res = call <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8> %data, <16 x i8> %key)
18 %res = call <16 x i8> @llvm.aarch64.crypto.aesd(<16 x i8> %data, <16 x i8> %key)
25 %res = call <16 x i8> @llvm.aarch64.crypto.aesmc(<16 x i8> %data)
32 %res = call <16 x i8> @llvm.aarch64.crypto.aesimc(<16 x i8> %data)
36 declare <4 x i32> @llvm.aarch64.crypto.sha1c(<4 x i32> %hash_abcd, i32 %hash_e, <4 x i32> %wk
[all...] |
| arm64-vqsub.ll | 1 ; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
8 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
17 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
26 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
35 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqsub.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
44 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqsub.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
53 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqsub.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
62 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqsub.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
71 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqsub.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
80 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2
[all...] |
| arm64-arith-saturating.ll | 8 %vqadd.i = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %vecext, i32 %vecext1) nounwind
17 %vqadd.i = tail call i64 @llvm.aarch64.neon.sqadd.i64(i64 %vecext, i64 %vecext1) nounwind
26 %vqadd.i = tail call i32 @llvm.aarch64.neon.uqadd.i32(i32 %vecext, i32 %vecext1) nounwind
35 %vqadd.i = tail call i64 @llvm.aarch64.neon.uqadd.i64(i64 %vecext, i64 %vecext1) nounwind
39 declare i64 @llvm.aarch64.neon.uqadd.i64(i64, i64) nounwind readnone
40 declare i32 @llvm.aarch64.neon.uqadd.i32(i32, i32) nounwind readnone
41 declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64) nounwind readnone
42 declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32) nounwind readnone
49 %vqsub.i = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %vecext, i32 %vecext1) nounwind
58 %vqsub.i = tail call i64 @llvm.aarch64.neon.sqsub.i64(i64 %vecext, i64 %vecext1) nounwin
[all...] |
| machine-copy-prop.ll | 1 ; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 -verify-machineinstrs < %s | FileCheck %s
21 %vmull = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> <i32 -1, i32 -1>, <2 x i32> %shuffle251)
32 %sqdmull = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> <i16 1, i16 0, i16 0, i16 0>, <4 x i16> <i16 2, i16 0, i16 0, i16 0>)
33 %sqadd = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> zeroinitializer, <4 x i32> %sqdmull)
40 call void @llvm.aarch64.neon.st2lane.v2i64.p0i8(<2 x i64> zeroinitializer, <2 x i64> zeroinitializer, i64 1, i8* %t1)
41 call void @llvm.aarch64.neon.st2lane.v1i64.p0i8(<1 x i64> <i64 4096>, <1 x i64> <i64 -1>, i64 0, i8* %t2)
42 %vld2_lane = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> <i64 11>, <1 x i64> <i64 11>, i64 0, i8* %t2)
45 %vld2_lane1 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0i8(<1 x i64> %vld2_lane.0.extract, <1 x i64> %vld2_lane.1.extract, i64 0, i8* %t1)
49 call void @llvm.aarch64.neon.st2.v1i64.p0i8(<1 x i64> %vld2_lane1.0.extract, <1 x i64> %vld2_lane1.1.extract, i8* %t3)
55 %sqadd1 = call <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64> <i64 -1>, <1 x i64> <i64 1>
[all...] |
| arm64-neon-aba-abd.ll | 3 declare <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8>, <8 x i8>)
4 declare <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8>, <8 x i8>)
8 %abd = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
15 %abd = call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
23 %abd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
30 %abd = call <8 x i8> @llvm.aarch64.neon.sabd.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
36 declare <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8>, <16 x i8>)
37 declare <16 x i8> @llvm.aarch64.neon.sabd.v16i8(<16 x i8>, <16 x i8>)
41 %abd = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
48 %abd = call <16 x i8> @llvm.aarch64.neon.uabd.v16i8(<16 x i8> %lhs, <16 x i8> %rhs
[all...] |
| arm64-ldxr-stxr.ll | 9 %ldrexd = tail call %0 @llvm.aarch64.ldxp(i8* %p)
26 %strexd = tail call i32 @llvm.aarch64.stxp(i64 %tmp4, i64 %tmp7, i8* %ptr)
30 declare %0 @llvm.aarch64.ldxp(i8*) nounwind
31 declare i32 @llvm.aarch64.stxp(i64, i64, i8*) nounwind
42 %val = call i64 @llvm.aarch64.ldxr.p0i8(i8* %addr)
56 %val = call i64 @llvm.aarch64.ldxr.p0i16(i16* %addr)
70 %val = call i64 @llvm.aarch64.ldxr.p0i32(i32* %addr)
82 %val = call i64 @llvm.aarch64.ldxr.p0i64(i64* %addr)
88 declare i64 @llvm.aarch64.ldxr.p0i8(i8*) nounwind
89 declare i64 @llvm.aarch64.ldxr.p0i16(i16*) nounwin
[all...] |
| /external/llvm/test/MC/AArch64/ |
| armv8.2a-mmfr2.s | 1 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
2 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
|
| armv8.2a-persistent-memory.s | 1 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.2a < %s | FileCheck %s
2 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.2a < %s 2>&1 | FileCheck %s --check-prefix=ERROR
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| armv8.2a-at.txt | 1 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.2a --disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.2a --disassemble < %s | FileCheck %s --check-prefix=NO_V82
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
| gc-relocs-257.d | 3 #ld: --defsym tempy=0x11012 --defsym tempy2=0x45034 --defsym tempy3=0x1234 -T aarch64.ld --gc-sections
10 .*: file format elf64-(little|big)aarch64
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 1 //===-- AArch6464FastISel.cpp - AArch64 FastISel implementation -----------===//
10 // This file defines the AArch64-specific support for the FastISel class. Some
16 #include "AArch64.h"
324 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass);
325 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
344 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
345 : &AArch64::GPR32RegClass;
346 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR;
370 unsigned Opc = Is64Bit ? AArch64::FMOVDi : AArch64::FMOVSi
[all...] |
| AArch64BranchRelaxation.cpp | 1 //===-- AArch64BranchRelaxation.cpp - AArch64 branch relaxation -----------===//
12 #include "AArch64.h"
27 #define DEBUG_TYPE "aarch64-branch-relax"
30 BranchRelaxation("aarch64-branch-relax", cl::Hidden, cl::init(true),
34 TBZDisplacementBits("aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
38 CBZDisplacementBits("aarch64-cbz-offset-bits", cl::Hidden, cl::init(19),
42 BCCDisplacementBits("aarch64-bcc-offset-bits", cl::Hidden, cl::init(19),
52 #define AARCH64_BR_RELAX_NAME "AArch64 branch relaxation pass"
115 INITIALIZE_PASS(AArch64BranchRelaxation, "aarch64-branch-relax",
239 BuildMI(OrigBB, DebugLoc(), TII->get(AArch64::B)).addMBB(NewBB)
[all...] |
| AArch64ConditionalCompares.cpp | 1 //===-- AArch64ConditionalCompares.cpp --- CCMP formation for AArch64 -----===//
20 #include "AArch64.h"
45 #define DEBUG_TYPE "aarch64-ccmp"
50 "aarch64-ccmp-limit", cl::init(30), cl::Hidden,
54 static cl::opt<bool> Stress("aarch64-stress-ccmp", cl::Hidden,
101 // instructions. The AArch64 conditional compare instructions have an immediate
260 if (DstReg == AArch64::WZR || DstReg == AArch64::XZR)
285 case AArch64::CBZW:
286 case AArch64::CBZX
[all...] |
| /external/clang/test/Preprocessor/ |
| aarch64-target-features.c | 1 // RUN: %clang -target aarch64-none-linux-gnu -x c -E -dM %s -o - | FileCheck %s
44 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crypto -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRYPTO %s
48 // RUN: %clang -target aarch64-none-linux-gnu -mcrc -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRC32 %s
50 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+crc -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-CRC32 %s
54 // RUN: %clang -target aarch64-none-linux-gnu -fno-math-errno -fno-signed-zeros\
57 // RUN: %clang -target aarch64-none-linux-gnu -ffast-math -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-FASTMATH %s
61 // RUN: %clang -target aarch64-none-linux-gnu -fshort-wchar -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SHORTWCHAR %s
65 // RUN: %clang -target aarch64-none-linux-gnu -fshort-enums -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-SHORTENUMS %s
69 // RUN: %clang -target aarch64-none-linux-gnu -march=armv8-a+simd -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-NEON %s
74 // RUN: %clang -target aarch64-none-eabi -march=armv8.1-a -x c -E -dM %s -o - | FileCheck --check-prefix=CHECK-V81A %
[all...] |
| /external/llvm/test/tools/llvm-readobj/ |
| reloc-types.test | 8 RUN: llvm-readobj -r -expand-relocs %p/Inputs/relocs.obj.elf-aarch64 | FileCheck %s -check-prefix ELF-AARCH64
152 ELF-AARCH64: Type: R_AARCH64_NONE (0)
153 ELF-AARCH64: Type: R_AARCH64_ABS64 (257)
154 ELF-AARCH64: Type: R_AARCH64_ABS32 (258)
155 ELF-AARCH64: Type: R_AARCH64_ABS16 (259)
156 ELF-AARCH64: Type: R_AARCH64_PREL64 (260)
157 ELF-AARCH64: Type: R_AARCH64_PREL32 (261)
158 ELF-AARCH64: Type: R_AARCH64_PREL16 (262)
159 ELF-AARCH64: Type: R_AARCH64_MOVW_UABS_G0 (263
[all...] |
| /device/linaro/hikey/uefi-tools/ |
| platforms.config | 15 # Currently supported are AARCH32 and AARCH64.
67 LONGNAME=aarch64 Juno
70 ARCH=AARCH64
79 LONGNAME=aarch64 FVP RTSM with full perhiperhal set
80 DSC=OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.dsc
81 BUILDFLAGS=-D EDK2_OUT_DIR=Build/ArmVExpress-FVP-AArch64-Full -D EDK2_ENABLE_SMSC_91X=1 -D EDK2_ENABLE_PL111=1
82 ARCH=AARCH64
84 UEFI_IMAGE_DIR=ArmVExpress-FVP-AArch64-Full
87 LONGNAME=aarch64 FVP RTSM
88 DSC=OpenPlatformPkg/Platforms/ARM/VExpress/ArmVExpress-FVP-AArch64.ds
[all...] |
| /external/clang/test/CodeGen/ |
| fp128_complex.c | 1 // RUN: %clang -target aarch64-linux-gnuabi %s -O3 -S -emit-llvm -o - | FileCheck %s
|
| le32-regparm.c | 2 // RUN: %clang_cc1 -triple aarch64 %s -fsyntax-only -verify
|
| neon-immediate-ubsan.c | 6 // RUN: %clang_cc1 -triple aarch64-unknown-unknown -emit-llvm -O1 -o - %s \
9 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=AARCH64
21 // CHECK-AARCH64: call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> {{.*}}, i32 1)
|
| /external/clang/test/Driver/ |
| aarch64-fixed-x18.c | 1 // RUN: %clang -target aarch64-none-gnu -ffixed-x18 -### %s 2> %t
|
